Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 43

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2.4 INTERFACE PROGRAMMING (Continued)
by not generating the interrupt until after the byte has been
read and then locking the FIFO, only one status read is
necessary. A DMA can be used to do all data transfers
(otherwise, it would be necessary to disable the DMA to
allow the CPU to read the status on each byte).
2-24
Error Handlin
Yes
Condition
No
No
No
(RR1 Bit 6)
(RR1 Bit 5)?
(RR1 Bit 7
(RR1 Bit 4)?
Special
Framing
Overrun
Parity
EOF
Is It
Is It
Is It
Is It
Figure 2-15. Special Conditions Interrupt Service Flow
No
Yes
1
Yes
Yes
No
Good Messag
Error Handlin
Error Handlin
(RR1 Bit 6)?
CRC Error
Is It
1
Consequently, since the special condition locks the FIFO
to preserve the status, it is necessary to issue the Error
Reset command to unlock it. Only the exit location of the
FIFO is locked allowing more data to be received into the
other bytes of the Receive FIFO.
1
1
Reset Highest IU
Error Handlin
Reads Dat
(WR0 - 38)
Characte
Ret
1
UM010901-06
01