Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 194

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

UM010901-0601
T
INTRODUCTION
Zilog’s customers need a way to evaluate its serial
communications controllers with a central CPU. This App
Note (Application Note) explains and illustrates how the
datacom family interfaces and communicates with the
80186 on this evaluation board. The board helps the
GENERAL DESCRIPTION
The evaluation board includes the following hardware.
(Reference two page Schematic diagram at rear of the App
Note - Figures 5A and 5B.)
Z
HE
Intel 80186 Integrated 16-bit Microprocessor
Zilog Z16C32 Integrated Universal Serial Controller
(IUSC™)
Zilog Z16C33 Monochannel Universal Serial Controller
(MUSC™) or USC
Zilog Z16C35 Integrated Serial Communications
Controller (ISCC™)
Zilog Z85230 Enhanced Serial Communications
Controller (ESCC™) or SCC
Two 28-pin EPROM sockets, suitable for 2764’s through
27512’s
Six 32-pin (or 28-pin) SRAM sockets, suitable for
32K x 8 or 128K x 8 devices
Z
ilog’s datacom family evaluation board features the 80186 along with four multiprotocol
serial controllers, and allows customers to evaluate these components in an Intel
environment.
ILOG
®
D
ATACOM
F
AMILY WITH THE
A
potential customer to evaluate Zilog’s data communications
controllers in an Intel environment.
The most advanced and complex component of the serial
family is the IUSC. One of the highlights of this App Note
is how the IUSC adapts to the 80186 CPU with a minimum
of difficulty and a maximum of bus and functional flexibility.
Notes:
All Signals with a preceding front slash, “/”, are active Low,
e.g.: B//W (WORD is active Low); /B/W (BYTE is active
Low, only).
Power connections follow conventional descriptions
below:
PPLICATION
Connection
Four Altera EPLD circuits comprising the glue logic
(Figures 1-4 at rear of the App Note) and Evaluation
Board Schematic (Figures 5a, 5b)
RS-232 and RS-422 line drivers and receivers
Pin headers for configuring and interconnecting the
above to serial applications
Ground
Power
N
OTE
Circuit
GND
V
CC
80186 CPU
Device
V
V
DD
SS
6-59
8
8