Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 215

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

Application Note
SCC in Binary Synchronous Communications
SYNCHRONOUS MODES
Three variations of character-oriented synchronous
communications are supported by the Z-SCC: Mono-sync,
Bisync, and External Sync (Figure 1). In Monosync mode,
a single sync character is transmitted, which is then
compared to an identical sync character in the receiver.
When the receiver recognizes this sync character,
synchronization is complete; the receiver then transfers
subsequent characters into the receiver FIFO in the Z-
SCC.
SYSTEM INTERFACE
The Z8002 Development Module consists of a Z8002 CPU,
16K words of dynamic RAM, 2K words of EPROM monitor,
a Z80A SIO providing dual serial ports, a Z80A CTC
peripheral device providing four counter/timer channels, two
Z80A PIO devices providing 32 programmable I/O lines,
and wire wrap area for prototyping. The block diagram is
depicted in Figure 2. Each of the peripherals in the
development module is connected in a prioritized daisy-
chain configuration. The Z-SCC is included in this
configuration by tying its IEI line to the IEO line of another
device, thus making it one stop lower in interrupt priority
compared to the other device.
6-80
Figure 1. Synchronous Modes of Communication
SYNC
SYNC
SYNC
SYNC Symbol
External
A. MONOSYNC Mode
B. BISYNC Mode
C. External SYNC Mode
DATA
DATA
DATA
DATA
DATA
DATA
CRC1
CRC1
CRC1
CRC2
CRC2
CRC2
Bisync mode uses a 16-bit or 12-bit sync character in the
same way to obtain synchronization. External Sync mode
uses an external signal to mark the beginning of the data
field; i.e., an external input pin (SYNC) indicates the start
of the information field.
In all synchronous modes, two Cyclic Redundancy Check
(CRC) bytes can be concatenated to the message to
detect data transmission errors. The CRC bytes inserted in
the transmitted message are compared to the CRC bytes
computed to the receiver. Any differences found are held
in the receive error FIFO.
Two Z8000 Development Modules containing Z-SCCs are
connected as shown in Figure 3 and Figure 4. The
Transmit Data pin of one is connected to the Receive Data
pin of the other and vice versa. The Z8002 is used as a
host CPU for loading the modules’ memories with software
routines.
The Z8000 CPU can address either of the two bytes
contained in 16-bit words. The CPU uses an even address
(16 bits) to access the most-significant byte of a word and
an odd address for the least-significant byte of a word.
UM010901-0601