Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 256
![IC 10MHZ Z8500 CMOS SCC 40-DIP](/photos/6/57/65796/269-40-dip_sml.jpg)
Z85C3010PSG
Manufacturer Part Number
Z85C3010PSG
Description
IC 10MHZ Z8500 CMOS SCC 40-DIP
Manufacturer
Zilog
Series
SCCr
Specifications of Z85C3010PSG
Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Cpu Speed
8MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
85
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3934
Z85C3010PSG
Z85C3010PSG
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UM010901-0601
TRANSMIT FIFO INTERRUPT
In the ESCC, transmit interrupt frequencies are reduced by
a deeper Transmit FIFO and the revised transmit interrupt
structure. If the WR7' D5 Transmit FIFO Interrupt Level bit
is reset, the transmit interrupt is generated when the entry
location of the FIFO is empty, i.e., more data can be
written. This is downward compatible with a SCC Transmit
Interrupt since the SCC only has a one-byte transmit buffer
instead of a four-byte Transmit FIFO.
Figure 4. Flowchart of Transmit Interrupt Service Routine to Reduce Transmit Interrupt Frequencies
Transmit FIFO
Transmit FIFO
With Data
Is Loaded
Full
NO
Boost Your System Performance Using The Zilog ESCC
TBE Interrupt
Transmit FIFO
Write Data To
Level Enabled
If WR7' D5 is set, the transmit buffer empty interrupt is
generated when the transmit FIFO is completely empty.
Enabling the transmit FIFO interrupt level, together with
polling the Transmit Buffer Empty (TBE) bit in RR0, causes
significant transmit interrupt frequency reduction. Transmit
data is sent in blocks of four bytes (algorithm is illustrated
in Figure 4). This helps to offload those systems which
have long interrupt latency or a fully loaded Operating
System.
TX FIFO Int.
TBE = '1'?
Service
RR0
YES
Application Note
6-121
™
1
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