Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 80

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

UM010901-0601
Note: For five or less bits per character selection in WR5, the
following encoding is used in the data sent to the transmitter.
D is the data bit(s) to be sent.
An additional bit, carrying parity information, may be auto-
matically appended to every transmitted character by set-
ting bit D0 of WR4 to 1. This bit is sent in addition to the
number of bits specified in WR4 or by bit D1 of WR4. If this
bit is set to 1, the transmitter sends even parity and, if set
to 0, the parity is odd.
The transmitter may be programmed to send a Break by
setting bit D4 of WR5 to 1. The transmitter will send con-
tiguous 0s from the first transmit clock edge after this com-
mand is issued, until the first transmit clock edge after this
bit is reset. The transmit clock edges referred to here are
those that defined transmitted bit cell boundaries. Care
must be taken when Break is sent. As mentioned above,
the SCC initiates the Break sequence regardless of the
character boundaries. Typically, the break sequence is de-
fined as “null character (all 0 data) with framing error”. The
other party may not be able to recognize it as a break se-
quence if the Send Break bit has been set in the middle of
sending a non-zero character.
An additional status bit for use in Asynchronous mode is
available in bit D0 of RR1. This bit, called All Sent, is set
when the transmitter is completely empty and any previous
data or stop bits have reached the TxD pin. The All Sent
bit can be used by the processor as an indication that the
transmitter may be safely disabled, or indication to change
the modem status signal.
The SCC may be programmed to accept a transmit clock
that is one, sixteen, thirty-two, or sixty-four times the data
rate. This is selected by bits D7 and D6 in WR4, in com-
mon with the clock factor for the receiver.
Note: When using Isosynchronous (X1 clock) mode, one-
and-a-half stop bits are not allowed. Only one or two stop
bits should be selected. If some length other than one stop
bit is desired in the times one mode, only two stop bits may
be used. Also, in this mode, the Transmitter usually needs
D7 D6 D5 D4 D3 D2 D1 D0
1
1
1
1
0
Bit 7
0
0
1
1
1
1
1
0
0
Table 4-2. Transmit Bits per Character
1
1
0
0
0
D
1
0
0
0
Bit 6
D
D
0
1
0
1
0
0
0
D
D
D
0
0
D
D
D
D
0
D
D
D
D
D
5 or less bits/character
7 bits/character
6 bits/character
8 bits/character
Sends one data bit
Sends two data bits
Sends three data bits
Sends four data bits
Sends five data bits
to send clocking information (transmit clock) along with the
data in order to receive data correctly.
There are two modem control signals associated with the
transmitter provided by the SCC; /RTS and /CTS.
The /RTS pin is a simple output that carries the inverted
state of the RTS bit (D1) in WR5, unless the Auto Enables
mode bit (D5) is set in WR3. When Auto Enables is set, the
/RTS pin immediately goes Low when the RTS bit is set.
However, when the RTS bit is reset, the /RTS pin remains
Low until the transmitter is completely empty and the last
stop bit has left the TxD pin. Thus, the /RTS pin may be
used to disable external drivers for the transmit data. The
/CTS pin is ordinarily a simple input to the CTS bit in RR0.
However, if Auto Enables mode is selected, this pin be-
comes an enable for the transmitter. That is, if Auto En-
ables is on and the /CTS pin is High, the transmitter is dis-
abled; the transmitter is enabled while the /CTS pin is Low.
The initialization sequence for the transmitter in Asynchro-
nous mode is WR4 first to select the mode, then WR3 and
WR5 to select the various options. At this point the other
registers should be initialized as necessary. When all of
this is complete, the transmitter may be enabled by setting
bit D3 of WR5 to 1. Note that the transmitter and receiver
may be initialized at the same time.
4.2.1.1 Asynchronous transmit on the NMOS/CMOS
On the NMOS/CMOS version of the SCC, characters are
loaded from the transmit buffer to the shift register where
they are given a start bit and a parity bit (as programmed),
and are shifted out to the TxD pin. The transmit buffer
empty interrupt and the DMA request (either /W//REQ or
/DTR//REQ pin) are asserted when the transmit buffer is
empty, if these are enabled. At this time, the CPU or the
DMA is able to write one byte of transmit data. The Trans-
mit Buffer Empty (TBE) bit (RR0, bit D2) also follows the
state of the transmit buffer. The All Sent bit, RR1, bit D0,
can be polled to determine when the last bit of transmit
data has cleared the TxD pin. For details about the trans-
mit DMA and transmit interrupts, refer to Section 2.4.8
“Transmit Interrupt and Transmit Buffer Empty bit.”
4.2.1.2 Asynchronous transmit on the ESCC
On the ESCC, characters are loaded from the Transmit
FIFO to the shift register where they are given a start bit
and a parity bit (as programmed), and are shifted out to the
TxD pin. The ESCC can generate an interrupt or DMA re-
quest depending on the status of the Transmit FIFO. If
WR7' D5 is reset, the transmit buffer empty interrupt and
DMA request (either /W//REQ or /DTR//REQ pin) are as-
serted when the entry location of the Transmit FIFO is
empty (one byte can be written). If WR7' D5 is set, the
transmit interrupt and DMA request is generated when the
Transmit FIFO is completely empty (four bytes can be writ-
ten). The Transmit Buffer Empty (TBE) bit in RR0, bit D2
also is affected by the state of WR7' bit D5. The All Sent
SCC™/ESCC™ User’s Manual
Data Communication Modes
4-5
4