Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 260

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

UM010901-0601
SDLC Frame Status FIFO enhancement is enabled by
setting WR15 D2. If it is enabled when EOF is detected,
byte count and status from the Status FIFO are loaded into
RR6, RR7 and RR1. This is used in DMA-driven systems.
Historically, EOF is treated as a special condition. Special
condition interrupts are triggered if any one of the below
interrupts is enabled:
1. Receive Interrupt on First Character or Special
2. Interrupt on All Receive Characters or Special
3. Special Receive Condition Only.
If 1 or 3 (above) is enabled, the data FIFO is locked after
the interrupt is serviced by reading RR1 in the Status
FIFO, as shown in Figure 11. This is commonly used in a
DMA-driven
information (e.g., EOF) to the data buffer. Locking the data
FIFO is not desirable in systems with long interrupt latency
Condition.
Conditions.
system
Data 1,N+1
Data n,N
EOF
to
avoid
Data n,N
Figure 9. Status FIFO Operation at End Of Frame
Packet 10
Packet 2
Packet 1
Enabled?
Packet N
delivering
Status
FIFO
FIFO Pointer
Increment
EOF
Byte Count
of Packet N
ESCC Receive
Data Flow Into
Data FIFO
Y
useless
(RRT = RR6)
Data 1,N+1
Byte Count
Boost Your System Performance Using The Zilog ESCC
Packet N+1
and high data rate communications. The reason is the
ERROR RESET command is necessary to unlock the
FIFO. Data from the next frame may be lost if ERROR
RESET fails to issue early.
This drawback is improved in the ESCC for a DMA driven
system. By enabling interrupts on “Special Receive
Conditions only” and SDLC status FIFO, EOF is treated
differently from other special conditions. When EOF status
reached the exit location of the FIFO:
1. A “Receive Data Available” interrupt is generated to
2. Receive Data FIFO is not locked.
Because of these changes, the data from the next frame is
securely loaded and the system processes the EOF
interrupt. The only responsibility of the software is issuing
the Reset Highest IUS before resuming normal operation
(Figure 12).
n
signal that EOF has been reached.
Status
(RR1)
FIFO Data
Available
Set
SDLC
Status
FIFO
Overflow If
Set FIFO
Required
Packet N
Status Is
Loaded
Application Note
6-125
™
1