Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 92

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

UM010901-0601
WR4
WR3
WR5
WR6
WR7
WR10
WR3
WR5
WR0
4.3.3 Transmitter/Receiver Synchronization
The SCC contains a transmitter-to-receiver synchronization
function that is used to guarantee that the character
boundaries for the received and transmitted data are the
same. In this mode, the receiver is in Hunt and the
transmitter is idle, sending either all 1s or all 0s. When the
There are several restrictions on the use of this feature in
the SCC. First, it only works with 6-bit, 8-bit or 16-bit sync
characters. The data character length for both the receiver
and the transmitter must be six bits with 6-bit sync charac-
ter, and eight bits with an 8-bit or 16-bit sync character. Of
course, the receive and transmit clocks must have the
same rate as well as the proper phase relationship.
Reg
D7
0
d
x
x
c
d
1
r
r
TxD
RxD
D6
0
0
0
x
x
x
x
t
t
Table 4-8. Initializing the Receiver in Character-Oriented Mode
D5
0
0
0
0
0
x
x
x
x
Figure 4-10. Transmitter to Receiver Synchronization
Bit Number
D4
x
1
0
x
x
0
1
0
0
D3
0
1
0
1
1
0
x
x
i
Sync
Sync
Direction of Message Flow
D2
0
0
0
0
0
0
0
x
x
D1
0
0
x
x
0
0
0
r
r
Sync
D0 Description
0
0
1
x
x
s
1
1
0
receiver recognizes a sync character, it leaves Hunt mode;
one character time later the transmitter is enabled and
begins sending sync characters. Beyond this point the
receiver and transmitter are again completely independent,
except that the character boundaries are now aligned
(Figure 4-10).
A specific sequence of operations must be followed to syn-
chronize the transmitter to the receiver. Both the receiver
and transmitter must have been initialized for operation in
Synchronous mode sometime in the past, although this ini-
tialization need not be redone each time the transmitter is
synchronized to the receiver. The transmitter is disabled
by setting bit D3 of WR5 to 0. At this point the transmitter
will send continuous 1s. If it is required that continuous
Receiver Leaves Hunt
Select x1 clock, enable sync mode, & no parity
x=0 for 8-bit sync, x=1 for 16-bit sync
rx=# of Rx bits/char, No auto enable, enter Hunt,
d=inverse state of DTR pin, tx=# of Tx bits/char,
use CRC-16, r=inverse state of /RTS pin, CRC enable
sync character, lower byte
sync character, upper byte
c=CRC preset, NRZ data, i=idle line condition
s=size of sync character
Enable Receiver
Enable Transmitter
Reset CRC generator
Enable Rx CRC, No sync character load inhibit
Sync
SCC™/ESCC™ User’s Manual
Data Communication Modes
4-17
4