Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 71

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

SCC™/ESCC™ User’s Manual
SCC/ESCC Ancillary Support Circuitry
3.4 DPLL DIGITAL PHASE-LOCKED LOOP (Continued)
In FM mode, the transmit clock and receive clock outputs
from the DPLL are not in phase. This is necessary to make
the transmit and receive bit cell boundaries coincide, since
the receive clock must sample the data one-fourth and
three-fourths of the way through the bit cell.
Ordinarily, a bit cell boundary occurs between count 15 or
count 16, and the DPLL receive output causes the data to
be sampled at one-fourth and three-fourths of the way
through the bit cell.
However, four variations can occur:
If the bit-cell boundary (from space to mark) occurs any-
where during the second half of count 15 or the first half of
count 16, the DPLL allows the transition without making a
correction to its count cycle.
If the bit-cell boundary (from space to mark) occurs be-
tween the middle of count 16 and the middle of count 19,
the DPLL is sampling the data too early in the bit cell. In
response to this, the DPLL extends its count by one during
the next 0 to 31 counting cycle, which effectively moves
the receive clock edges closer to where they should be.
Any transitions occurring between the middle of count 19
in one cycle and the middle of count 12 during the next cy-
cle are ignored by the DPLL. This guarantees that any data
transitions in the bit cells do not cause an adjustment to the
counting cycle.
If no transition occurs between the middle of count 12 and
the middle of count 19, the DPLL is probably not locked
onto the data properly. When the DPLL misses an edge,
the One Clock Missing bit is RR10, it is set to 1 and
latched. It will hold this value until a Reset Missing Clock
command is issued in WR14, or until the DPLL is disabled
or programmed to enter the Search mode. Upon missing
this one edge, the DPLL takes no other action and does
not modify its count during the next counting cycle.
If the DPLL does not see an edge between the middle of
count 12 and the middle of count 19 in two successive 0 to
31 count cycles, a line error condition is assumed. If this
occurs, the Two Clocks Missing bit in RR10 is set to 1 and
latched. At the same time, the DPLL enters the Search
mode. The DPLL makes the decision to enter the Search
mode during count 2, where both the receive clock and
transmit clock outputs are Low. This prevents any glitches
on the clock outputs when the Search mode is entered.
While in the Search mode, no clock outputs are provided
by the DPLL. The Two Clocks Missing bit in RR10 is
latched until a Reset Missing Clock command is issued in
WR14, or until the DPLL is disabled or programmed to en-
ter the Search mode.
3-10
While the DPLL is disabled, the transmit clock output of the
DPLL may be toggled by alternately selecting FM and
NRZI mode in the DPLL. The same is true of the receive
clock.
While the DPLL is in the Search mode, the counter re-
mains at count 16 where the receive output is Low and the
transmit output is Low. This fact is used to provide a trans-
mit clock under software control since the DPLL is in the
Search mode while it is disabled.
As in NRZI mode, if an adjustment to the counting cycle is
necessary, the DPLL modifies count 5, either deleting it or
doubling it. If no adjustment is necessary, the count se-
quence proceeds normally.
When the DPLL is programmed to enter Search mode,
only clock transitions should exist on the receive data pin.
If this is not the case, the DPLL may attempt to lock on to
the data transitions. If the DPLL does lock on to the data
transitions, then the Missing Clock condition will inevitably
occur because data transitions are not guaranteed every
bit cell.
To lock in the DPLL properly, FM0 encoding requires con-
tinuous 1s received when leaving the Search mode. In
FM1 encoding, continuous 0s are required; with Manches-
ter encoded data this means alternating 1s and 0s. With all
three of these data encoding methods there is always at
least one transition in every bit cell, and in FM mode the
DPLL is designed to expect this transition.
3.4.3 DPLL Operation in the Manchester
Mode
The SCC can be used to decode Manchester data by us-
ing the DPLL in the FM mode and programming the receiv-
er for NRZ data. Manchester encoded data contains a
transition at the center of every bit cell; it is the direction of
this transition that distinguishes a 1 from a 0. Hence, for
Manchester data, the DPLL should be in FM mode (WR14
command D7=1, D6=1, D5=0), but the receiver should be
set up to accept NRZ data (WR10 D6=0, D5=0).
3.4.4 Transmit Clock Counter (ESCC only)
The ESCC includes a Transmit Clock Counter which par-
allels the DPLL. This counter provides a jitter-free clock
source to the transmitter by dividing the DPLL clock source
by the appropriate value for the programmed data encod-
ing format as shown in Figure 3-9. Therefore, in FM mode
(FM0 or FM1), the counter output is the input frequency di-
vided by 16. In NRZI mode, the counter frequency is the in-
put divided by 32. The counter output replaces the DPLL
transmit clock output, available as the transmit clock
source. This has no effect on the use of the DPLL as the
receive clock source.
UM010901-0601