Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 98

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

UM010901-0601
by the processor issuing the Enter Hunt mode command in
WR3. This bit (D4) is a command, and writing a 0 to it has
no effect. The Hunt status of the receiver is reported by the
Sync/Hunt bit in RR0.
Sync/Hunt is one of the possible sources of external/status
interrupts, with both transitions causing an interrupt. This
is true even if the Sync/Hunt bit is set as a result of the pro-
cessor issuing the Enter Hunt mode command.
The SCC assumes the first byte in an SDLC frame is the
address of the secondary station for which the frame is in-
tended. The SCC provides several options for handling
this address.
If the Address Search Mode bit (D2) in WR3 is set to 0, the
address recognition logic is disabled and all received
frames are transferred to the receive data FIFO. In this
mode the software must perform any address recognition.
If the Address Search Mode bit is set to 1, only those
frames whose address matches the address programmed
in WR6 or the global address (all 1s) will be transferred to
the receive data FIFO.
The address comparison is across all eight bits of WR6 if
the Sync Character Load inhibit bit (D1) in WR3 is set to 0.
The comparison may be modified so that only the four
most significant bits of WR6 match the received address.
This mode is selected by setting the Sync Character Load
inhibit bit to 1. In this mode, however, the address field is
still eight bits wide. The address field is transferred to the
receive data FIFO in the same manner as data. It is not
treated differently than data.
/SYNC
/RTxC
PCLK
Figure 4-12. /SYNC as an Output
The receiver automatically enters Hunt mode if an abort is
received. Because the receiver always searches the
receive data stream for flags, and automatically enters
Hunt Mode when an abort is received, the receiver always
handles frames correctly. The Enter Hunt Mode command
should never be needed. The SCC drives the /SYNC pin
Low to signal that a flag has been recognized. The timing
for the /SYNC signal is shown in Figure 4-12.
The number of bits per character is controlled by bits D7
and D6 of WR3. Five, six, seven, or eight bits per character
may be selected via these two bits. The data is right-justi-
fied in the receive buffer. The SCC merely takes a snap-
shot of the receive data stream at the appropriate times, so
the “unused” bits in the receive buffer are only the bits fol-
lowing the character.
An additional bit carrying parity information is selected by
setting bit D6 of WR4 to 1. This also enables parity in the
transmitter. The parity sense is selected by bit D1 of WR4.
Parity is not normally used in SDLC mode.
The character length can be changed at any time before
the new number of bits have been assembled by the
receiver. Care should be exercised, however, as
unexpected results may occur. A representative example,
switching from five bits to eight bits and back to five bits, is
shown in Figure 4-13.
State Changes in One
/RTxC Clock Cycle
SCC™/ESCC™ User’s Manual
Data Communication Modes
4-23
4