KSZ8851-32MQLI Micrel Inc, KSZ8851-32MQLI Datasheet - Page 31

• Manufacturer Part Number: KSZ8851-32MQLI
• Description: IC CTLR MAC/PHY NON PCI 128PQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8851-32MQLI

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Bus
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 576-3630; KSZ8851-32MQLI

Clock Generator
The X1 and X2 pins are connected to a 25 MHz crystal. X1 can also serve as the connector to a 3.3V, 25 MHz oscillator
(as described in the pin description).
Bus Interface Unit (BIU)
The BIU host interface is a generic bus interface, designed to communicate with embedded processors. No glue logic is
required when it talks to various standard asynchronous buses and processors.
Supported Transfers
In terms of transfer type, the BIU can support asynchronous transfer or SRAM-like slave mode. To support the data
transfers, the BIU provides a group of signals:
Asynchronous or SRAM-like signals: Address/Data (A[7:1]/D[15:0]), Address Enable (AEN), Read (RDN), Write (WRN),
Byte Enable (BE[3:0]N), Async Ready (ARDY) and Interrupt (INTRN).
Physical Data Bus Size
The BIU supports an 8-bit, 16-bit or 32-bit host standard data bus. Depending on the size of the physical data bus, the
KSZ8851M can support 8-bit, 16-bit or 32-bit data transfers.
For example,
For a 32-bit system/host data bus, the KSZ8851-32MQL allows an 8-bit, 16-bit and 32-bit data transfer.
For a 16-bit system/host data bus, the KSZ8851-16MQL allows an 8-bit and 16-bit data transfer.
For an 8-bit system/host data bus, the KSZ8851-16MQL only allows an 8-bit data transfer.
The KSZ8851M supports internal data byte-swap and word-swap. This means that the system/host data bus HD[7:0] just
connect to D[7:0] for an 8-bit data bus interface. For a 16-bit data bus, the system/host data bus HD[15:8] and HD[7:0]
only need to connect to D[15:8] and D[7:0] respectively.
Table 4 describes the BIU signal grouping.
August 2009
Micrel, Inc.
Notes:
1. Bit 0 (RX Enable), Bit 5 (RX Unicast Enable) and Bit 6 (RX Multicast Enable) must set to 1 in RXCR1 register.
2. The KSZ8851M will discard frame with SA same as the MAC address if bit[0] is set in RXCR2 register.
Signal
A[7:1]
D[15:0]
D[31:16]
10
11
9
Perfect with
Multicast
address
passed
Hash only with
Physical
address
passed
Perfect with
Physical
address
passed
Type
Input
I/O
I/O
1
1
1
Function
Address Bus
Data Bus, For both KSZ8851-32MQL and KSZ8851-16MQL devices.
Data Bus, For KSZ8851-32MQL device only.
0
0
0
Table 3. Address Filtering Scheme
1
1
0
31
1
0
1
All Rx frames are passed with Physical
address (DA) matching the MAC address and
with Multicast address without any conditions.
All Rx frames are passed with Multicast
address matching the MAC address hash
table and with Physical address without any
conditions.
All Rx frames are passed with Multicast
address matching the MAC address and with
Physical address without any conditions.
KSZ8851-16/32 MQL/MQLI
M9999-083109-2.0