KSZ8851-32MQLI Micrel Inc, KSZ8851-32MQLI Datasheet - Page 34

• Manufacturer Part Number: KSZ8851-32MQLI
• Description: IC CTLR MAC/PHY NON PCI 128PQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8851-32MQLI

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Bus
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 576-3630; KSZ8851-32MQLI

The transmit Byte Count specifies the total number of bytes to be transmitted from the TXQ. Its format is given in Table 7.
The data area contains six bytes of Destination Address (DA) followed by six bytes of Source Address (SA), followed by a
variable-length number of bytes. On transmit, all bytes are provided by the CPU, including the source address. The
KSZ8851M does not insert its own SA. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the
KSZ8851M. It is treated transparently as data both for transmit operations.
Frame Transmitting Path Operation in TXQ
This section describes the typical register settings for transmitting packets from host processor to KSZ8851M with generic
bus interface. User can use the default value for most of the transmit registers. The following Table 8 describes all
registers which need to be set and used for transmitting single or multiple frames.
August 2009
Register Name
[bit](offset)
TXCR[3:0](0x70)
TXCR[8:5](0x70)
TXMIR[12:0](0x78)
TXQCR[0](0x80)
TXQCR[1](0x80)
TXQCR[2](0x80)
Micrel, Inc.
Bit
15-11
10-0
Bit
15
14-6
5-0
Description
Reserved.
TXBC Transmit Byte Count
Transmit Byte Count. Hardware uses the byte count information to conserve the TX buffer memory for
better utilization of the packet memory.
Note: The hardware behavior is unknown if an incorrect byte count information is written to this field.
Writing a 0 value to this field is not permitted.
Description
TXIC Transmit Interrupt on Completion
When this bit is set, the KSZ8851M sets the transmit interrupt after the present frame has been
transmitted.
Reserved.
TXFID Transmit Frame ID
This field specifies the frame ID that is used to identify the frame and its associated status information
in the transmit status register.
Set transmit control function as below:
Set bit 3 to enable transmitting flow control. Set bit 2 to enable transmitting padding.
Set bit 1 to enable transmitting CRC. Set bit 0 to enable transmitting block operation.
Set transmit checksum generation for ICMP, UDP, TCP and IP packet.
The amount of free transmit memory available is represented in units of byte. The TXQ memory (6 KByte) is
used for both frame payload and control word.
For single frame to transmit, set this bit 0 = 1(manual enqueue). the KSZ8851M will enable current TX frame
prepared in the TX buffer is queued for transmit, this is only transmit one frame at a time.
Note: This bit is self-clearing after the frame is finished transmitting. The software should wait for the bit to
be cleared before setting up another new TX frame.
When this bit is written as 1, the KSZ8851M will generate interrupt (bit 6 in ISR register) to CPU when TXQ
memory is available based upon the total amount of TXQ space requested by CPU at TXNTFSR (0x9E)
register.
Note: This bit is self-clearing after the frame is finished transmitting. The software should wait for the bit to
be cleared before set to 1 again
For multiple frames to transmit, set this bit 2 = 1 (auto-enqueue). the KSZ8851M will enable current all TX
frames prepared in the TX buffer are queued to transmit automatically.
Table 6. Transmit Control Word Bit Fields
Table 7. Transmit Byte Count Format
34
Description
KSZ8851-16/32 MQL/MQLI
M9999-083109-2.0