KSZ8851-32MQLI Micrel Inc, KSZ8851-32MQLI Datasheet - Page 68

• Manufacturer Part Number: KSZ8851-32MQLI
• Description: IC CTLR MAC/PHY NON PCI 128PQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8851-32MQLI

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Bus
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 576-3630; KSZ8851-32MQLI

0xB6 – 0xBF: Reserved
Chip ID and Enable Register (0xC0 – 0xC1): CIDER
This register contains the chip ID and the chip enable bit.
0xC2 – 0xC5: Reserved
Chip Global Control Register (0xC6 – 0xC7): CGCR
This register contains the global control for the chip function.
Indirect Access Control Register (0xC8 – 0xC9): IACR
This register contains the indirect control for the MIB counter (Write IACR triggers a command. Read access is
determined by bit 12).
August 2009
Micrel, Inc.
Bit
15-8
7-4
3-1
0
Bit
15
14-12
11-10
9
8
7-0
Bit
15-13
12
0x0
0x0
0x0
0x0
0x0
Default
0x88
0x7
0x1
Default
0x0
0x2
0x35
Default
0x0
R/W
RW
RW
RW
RW
R/W
RW
R/W
RW
RW
R/W
RO
RO
RO
RW
These bits are used to define the QMU RX queue overrun watermark configuration. It is in
double words count and default is 256 Bytes available buffer space out of 12 Kbyte.
Description
Family ID
Chip family ID
Chip ID
0x7 is assigned to KSZ8851-16/32MQL
Revision ID
Reserved
Description
LEDSEL1
See description for bit 9.
Reserved.
Reserved.
LEDSEL0
This bit sets the LEDSEL0 selection and bit 15 sets the LEDSEL1 selection.
PHY port LED indicators, defined as below:
Reserved.
Reserved.
Description
Reserved.
Read Enable.
P1LED3
P1LED2
P1LED1
P1LED0
P1LED3
P1LED2
P1LED1
P1LED0
[0, 0]
------
LINK/ACT
FULL_DPX/COL
SPEED
[1, 0]
ACT
LINK
FULL_DPX/COL
SPEED
[LEDSEL1 (bit15), LEDSEL0 (bit9)]
[LEDSEL1, LEDSEL0]
68
[0, 1]
------
100LINK/ACT
10LINK/ACT
FULL_DPX
[1, 1]
NA
NA
NA
NA
KSZ8851-16/32 MQL/MQLI
M9999-083109-2.0