KSZ8851-32MQLI Micrel Inc, KSZ8851-32MQLI Datasheet - Page 32

• Manufacturer Part Number: KSZ8851-32MQLI
• Description: IC CTLR MAC/PHY NON PCI 128PQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8851-32MQLI

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Bus
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 576-3630; KSZ8851-32MQLI

Note: The LDEVN output signal will be asserted to indicate that the KSZ8851M is successfully targeted. The signal
LDEVN is a combinatorial decode of AEN and A[7:1].
Little and Big Endian Support
The KSZ8851M supports either Little- or Big-Endian microprocessor. The external strap pin 29 (EESK) is used to select
between two modes. The KSZ8851M operates in Little Endian when this pin is pulled-down or in Big Endian when this pin
is pulled-up.
When this pin 29 is no connect or tied to GND, the bit 11 (Endian mode selection) in RXFDPR register can be used to
program either Little (bit11=0) Endian mode or Big (bit11=1) Endian mode.
Asynchronous Interface
For asynchronous transfers, the asynchronous interface uses RDN (read) and WRN (write) signal strobes for data
latching. If necessary, ARDY is de-asserted on the falling edge of the strobe.
All asynchronous transfers are either single-data or burst-data transfers. Byte, word, and double word data buses and
accesses (transfers) are supported. The BIU, however, provides flexible asynchronous interfacing to communicate with
various applications and architectures. No additional address latch is required. The BIU decodes A[7:1] and qualifies with
AEN (Address Enable) to determine if the KSZ8851M device is the intended target. The host utilizes the rising edge of
RDN to latch read data and the KSZ8851M will use falling edge of WRN to latch write data.
BIU Summation
Figure 7 shows the connection for different data bus sizes. Also refer to reference schematics in hardware design
package.
Note: For the 8-bit data bus mode, the internal inverter is enabled and connected between BE0N and BE1N, so an even
address will enable the BE0N and an odd address will enable the BE1N.
Strapping Options:
EESK (pin 29, Ipd/O): Pull-down or no connect (default) selects Little Endian. Pull-up selects Big Endian.
EEDI (pin 30, Ipd): Pull-down or no connect (default) selects 8-bit bus mode. Pull-up selects 16-bit bus mode.
August 2009
Micrel, Inc.
Signal
AEN
BE3N, BE2N,
BE1N, BE0N
INTRN
RDN
WRN
ARDY
Type
Input
Input
Output
Input
Input
Output
Function
Address Enable
Address Enable asserted indicates memory address on the bus for DMA access and since the
device is an I/O device, address decoding is only enabled when AEN is Low.
Byte Enable
Interrupt
Asynchronous Read
Asynchronous Write
Asynchronous Ready, This signal is asserted (Low) to ask CPU inserting wait state.
BE0N
0
0
1
0
1
1
1
Table 4. Bus Interface Unit Signal Grouping
BE1N
0
0
1
1
0
1
1
BE2N
0
1
0
1
1
0
1
32
0
1
0
1
1
1
0
BE3N
Description
32-bit access
Lower 16-bit (D[15:0]) access
Higher 16-bit (D[31:16]) access
Byte 0 (D[7:0]) access
Byte 1 (D[15:8]) access
Byte 2 (D[23:16]) access
Byte 3 (D[31:24]) access
KSZ8851-16/32 MQL/MQLI
M9999-083109-2.0