KSZ8851-32MQLI Micrel Inc, KSZ8851-32MQLI Datasheet - Page 61

• Manufacturer Part Number: KSZ8851-32MQLI
• Description: IC CTLR MAC/PHY NON PCI 128PQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8851-32MQLI

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Bus
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 576-3630; KSZ8851-32MQLI

Receive Frame Header Byte Count Register (0x7E – 0x7F): RXFHBCR
This register indicates the received frame header byte count information, the received frames are reported in RXFCTR
register. This register contains the total number of bytes information for the frame received and the CPU can read so
many times same as the frame count value in the RXFCTR.
TXQ Command Register (0x80 – 0x81): TXQCR
This register is programmed by the Host CPU to issue a transmit command to the TXQ. The present transmit frame in
the TXQ memory is queued for transmit.
RXQ Command Register (0x82 – 0x83): RXQCR
This register is programmed by the Host CPU to issue DMA read or write command to the RXQ and TXQ. This register
also is used to control all RX thresholds enable and status.
August 2009
Micrel, Inc.
Bit
1
0
Bit
15-12
11-0
Bit
15-3
2
1
0
Bit
15-13
12
11
-
-
-
-
-
0x0
0x0
0x0
-
-
-
Default Value
Default Value
Default Value
Default Value
R/W
RO
RO
R/W
RO
RO
R/W
RW
RW
RW
RW
R/W
RW
RO
RO
Description
RXRF Receive Runt Frame
When this bit is set, it indicates that a frame was damaged by a collision or had a
premature termination before the collision window passed.
Runt frames are passed to the host only if the pass bad frame bit is set.
RXCE Receive CRC Error
When this bit is set, it indicates that a CRC error has occurred on the current received
frame.
CRC error frames are passed to the host only if the pass bad frame bit is set.
Description
Reserved.
RXBC Receive Byte Count
This field indicates the present received frame byte size.
Description
Reserved
AETFE Auto-Enqueue TXQ Frame Enable
When this bit is written as 1, the KSZ8851M will enable current all TX frames prepared in
the TX buffer are queued to transmit automatically.
The bit 0 METFE has to be set 0 when this bit is set to 1 in this register.
TXQMAM TXQ Memory Available Monitor
When this bit is written as 1, the KSZ8851M will generate interrupt (bit 6 in ISR register) to
CPU when TXQ memory is available based upon the total amount of TXQ space
requested by CPU at TXNTFSR (0x9E) register.
Note: This bit is self-clearing after the frame is finished transmitting. The software should
wait for the bit to be cleared before set to 1 again.
METFE Manual Enqueue TXQ Frame Enable
When this bit is written as 1, the KSZ8851M will enable current TX frame prepared in the
TX buffer is queued for transmit, this is only transmit one frame at a time.
Note: This bit is self-clearing after the frame is finished transmitting. The software should
wait for the bit to be cleared before setting up another new TX frame.
Description
Reserved.
RXDTTS RX Duration Timer Threshold Status
When this bit is set, it indicates that RX interrupt is due to the time start at first received
frame in RXQ buffer exceeds the threshold set in RX Duration Timer Threshold Register
(0x8C, RXDTT).
This bit will be updated when write 1 to bit 13 in ISR register.
RXDBCTS RX Data Byte Count Threshold Status
When this bit is set, it indicates that RX interrupt is due to the number of received bytes in
RXQ buffer exceeds the threshold set in RX Data Byte Count Threshold Register (0x8E,
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KSZ8851-16/32 MQL/MQLI
M9999-083109-2.0