KSZ8851-32MQLI Micrel Inc, KSZ8851-32MQLI Datasheet - Page 62

• Manufacturer Part Number: KSZ8851-32MQLI
• Description: IC CTLR MAC/PHY NON PCI 128PQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8851-32MQLI

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Bus
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 576-3630; KSZ8851-32MQLI

TX Frame Data Pointer Register (0x84 – 0x85): TXFDPR
The value of this register determines the address to be accessed within the TXQ frame buffer. When the AUTO increment
is set, It will automatically increment the pointer value on write accesses to the data register.
The counter is incremented by one for every byte access, by two for every word access, and by four for every double
word access.
August 2009
Micrel, Inc.
10
9
8
7
6
5
4
3
2-1
0
-
0x0
-
0x0
0x0
0x0
0x0
0x0
-
0x0
RO
RW
RW
RW
RW
RW
RW
WO
RW
RW
RXDBCT).
This bit will be updated when write 1 to bit 13 in ISR register.
RXFCTS RX Frame Count Threshold Status
When this bit is set, it indicates that RX interrupt is due to the number of received frames
in RXQ buffer exceeds the threshold set in RX Frame Count Threshold Register (0x9C,
RXFCT).
This bit will be updated when write 1 to bit 13 in ISR register.
RXIPHTOE RX IP Header Two-Byte Offset Enable
When this bit is written as 1, the KSZ8851M will enable to add two bytes before frame
header in order for IP header inside the frame contents to be aligned with double word
boundary to speed up software operation.
Reserved.
RXDTTE RX Duration Timer Threshold Enable
When this bit is written as 1, the KSZ8851M will enable RX interrupt (bit 13 in ISR) when
the time start at first received frame in RXQ buffer exceeds the threshold set in RX
Duration Timer Threshold Register (0x8C, RXDTT).
RXDBCTE RX Data Byte Count Threshold Enable
When this bit is written as 1, the KSZ8851M will enable RX interrupt (bit 13 in ISR) when
the number of received bytes in RXQ buffer exceeds the threshold set in RX Data Byte
Count Threshold Register (0x8E, RXDBCT).
RXFCTE RX Frame Count Threshold Enable
When this bit is written as 1, the KSZ8851M will enable RX interrupt (bit 13 in ISR) when
the number of received frames in RXQ buffer exceeds the threshold set in RX Frame
Count Threshold Register (0x9C, RXFCT).
ADRFE Auto-Dequeue RXQ Frame Enable
When this bit is written as 1, the KSZ8851M will automatically enable RXQ frame buffer
dequeue. The read pointer in RXQ frame buffer will be automatically adjusted to next
received frame location after current frame is completely read by the host.
SDA Start DMA Access
When this bit is written as 1, the KSZ8851M allows a DMA operation from the host CPU
to access either read RXQ frame buffer or write TXQ frame buffer with AEN, RDN or
WRN signals regardless of the address and byte enable signals. All registers access are
disabled except this register during this DMA operation.
This bit must be set to 0 when DMA operation is finished in order to access the rest of
registers.
Reserved.
RRXEF Release RX Error Frame
When this bit is written as 1, the current RX error frame buffer is released.
Note: This bit is self-clearing after the frame memory is released. The software should
wait for the bit to be cleared before processing new RX frame.
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KSZ8851-16/32 MQL/MQLI
M9999-083109-2.0