KSZ8851-32MQLI Micrel Inc, KSZ8851-32MQLI Datasheet - Page 66

• Manufacturer Part Number: KSZ8851-32MQLI
• Description: IC CTLR MAC/PHY NON PCI 128PQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8851-32MQLI

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Bus
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 576-3630; KSZ8851-32MQLI

0x94 – 0x9B: Reserved
RX Frame Count & Threshold Register (0x9C – 0x9D): RXFCTR
This register indicates the current total amount of received frame count in RXQ frame buffer and also is used to program
the received frame count threshold.
TX Next Total Frames Size Register (0x9E – 0x9F): TXNTFSR
This register is used by the host CPU to program the total amount of TXQ buffer space requested for the next transmit.
MAC Address Hash Table Register 0 (0xA0 – 0xA1): MAHTR0
The 64-bit MAC address table is used for group address filtering and it is enabled by selecting item 5 “Hash perfect” mode
in Table 3 (Address Filtering Scheme).
This value is defined as the six most significant bits from CRC circuit calculation result that is based on 48-bit of DA input.
The two most significant bits select one of the four registers to be used, while the others determine which bit within the
register.
Multicast table register 0.
MAC Address Hash Table Register 1 (0xA2 – 0xA3): MAHTR1
Multicast table register 1.
August 2009
Micrel, Inc.
Bit
2
1
0
Bit
15-8
7-0
Bit
15-0
Bit
15-0
0x0
0x0
0x0
Default Value
Default Value
0x00
0x00
Default Value
0x0000
Default Value
0x0
R/W
RO
RO
RO
R/W
RO
RW
R/W
RW
R/W
RW
Description
RXFC RX Frame Count
To indicate the total received frames in RXQ frame buffer when receive interrupt (bit13=1
in ISR) occurred and write “1” to clear this bit 13 in ISR. The host CPU can start to read
the updated receive frame header information in RXFHSR/RXFHBCR registers after read
this RX frame count register.
RXFCT Receive Frame Count Threshold
To program received frame count threshold value.
When bit 5 set to 1 in RXQCR register, the KSZ8851M will set RX interrupt (bit 13 in ISR)
when the number of received frames in RXQ buffer exceeds the threshold set in this
register.
Description
TXNTFS TX Next Total Frames Size
The host CPU is used to program the total amount of TXQ buffer space which is required
for next total transmit frames size in double-word count.
When bit 1 (TXQ memory available monitor) is set to 1 in TXQCR register, the KSZ8851M
will generate interrupt (bit 6 in ISR register) to CPU when TXQ memory is available based
upon the total amount of TXQ space requested by CPU at this register.
Description
HT0 Hash Table 0
When the appropriate bit is set, if the packet received with DA matches the CRC, the
hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Description
When this bit is set, it indicates that wake-up from linkup detect status has occurred.
Write “0010” to PMECR[5:2] to clear this bit.
EDIS Energy Detect Interrupt Status
When this bit is set and bit 2=1, bit 0=0 in IER register, it indicates that wake-up from
energy detect status has occurred. When this bit is set and bit 2, 0=1 in IER register, it
indicates that wake-up from delay energy detect status has occurred.
Write “0001” to PMECR[5:2] to clear this bit.
Reserved
Reserved
66
KSZ8851-16/32 MQL/MQLI
M9999-083109-2.0