KSZ8851-32MQLI Micrel Inc, KSZ8851-32MQLI Datasheet - Page 58

• Manufacturer Part Number: KSZ8851-32MQLI
• Description: IC CTLR MAC/PHY NON PCI 128PQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8851-32MQLI

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Bus
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 576-3630; KSZ8851-32MQLI

Transmit Status Register (0x72 – 0x73): TXSR
This register keeps the status of the last transmitted frame.
Receive Control Register 1 (0x74 – 0x75): RXCR1
This register holds control information programmed by the CPU to control the receive function.
August 2009
Micrel, Inc.
Bit
1
0
Bit
15-14
13
12
11-6
5-0
Bit
15
14
13
12
11
10
9
0x0
0x0
0x0
0x0
-
-
0x0
0x0
0x0
0x0
0x1
0x0
0x0
Default Value
Default Value
0x0
Default Value
R/W
RW
RW
R/W
RO
RO
RO
RO
RO
R/W
RW
RW
RW
RW
RW
RW
RW
Description
Reserved.
TXLC Transmit Late Collision
This bit is set when a transmit Late Collision occurs.
TXMC Transmit Maximum Collision
This bit is set when a transmit Maximum Collision is reached.
Reserved.
TXFID Transmit Frame ID
This field identifies the transmitted frame. All of the transmit status information in this
register belongs to the frame with this ID.
Description
FRXQ Flush Receive Queue
When this bit is set, The receive queue memory is cleared and RX frame pointer is reset.
Note: Disable the RXE receive enable bit[0] first before set this bit, then clear this bit to
normal operation.
RXUDPFCC Receive UDP Frame Checksum Check Enable
When this bit is set, the KSZ8851 will check for correct UDP checksum for incoming UDP
frames. Any received UDP frames with incorrect checksum will be discarded.
RXTCPFCC Receive TCP Frame Checksum Check Enable
When this bit is set, the KSZ8851 will check for correct TCP checksum for incoming TCP
frames. Any received TCP frames with incorrect checksum will be discarded.
RXIPFCC Receive IP Frame Checksum Check Enable
When this bit is set, the KSZ8851 will check for correct IP header checksum for incoming
IP frames. Any received IP header with incorrect checksum will be discarded.
RXPAFMA Receive Physical Address Filtering with MAC Address Enable
When this bit is set, this bit enables the RX function to receive physical address that pass
the MAC address filtering mechanism (see Address Filtering Scheme in Table 3 for
detail).
RXFCE Receive Flow Control Enable
When this bit is set and the KSZ8851M is in full-duplex mode, flow control is enabled, and
the KSZ8851M will acknowledge a PAUSE frame from the receive interface; i.e., the
outgoing packets are pending in the transmit buffer until the PAUSE frame control timer
expires. This field has no meaning in half-duplex mode and should be programmed to 0.
When this bit is cleared, flow control is not enabled.
RXEFE Receive Error Frame Enable
When this bit is set, CRC error frames are allowed to be received into the RX queue.
When this bit is cleared, all CRC error frames are discarded.
Description
TXCE Transmit CRC Enable
When this bit is set, the KSZ8851M automatically adds a 32-bit CRC checksum field to
the end of a transmit frame.
TXE Transmit Enable
When this bit is set, the transmit module is enabled and placed in a running state. When
reset, the transmit process is placed in the stopped state after the transmission of the
current frame is completed.
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KSZ8851-16/32 MQL/MQLI
M9999-083109-2.0