KSZ8851-32MQLI Micrel Inc, KSZ8851-32MQLI Datasheet - Page 49

IC CTLR MAC/PHY NON PCI 128PQFP

KSZ8851-32MQLI

Manufacturer Part Number
KSZ8851-32MQLI
Description
IC CTLR MAC/PHY NON PCI 128PQFP
Manufacturer
Micrel Inc
Datasheet

Specifications of KSZ8851-32MQLI

Controller Type
Ethernet Controller, MAC/PHY
Interface
Bus
Voltage - Supply
1.8V, 2.5V, 3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
128-MQFP, 128-PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Other names
576-3630
KSZ8851-32MQLI

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
KSZ8851-32MQLI
Manufacturer:
Micrel Inc
Quantity:
10 000
Register Map: MAC, PHY and QMU
Do not write to bit values or to registers defined as Reserved. Manipulating reserved bits or registers causes
unpredictable and often fatal results. If the user wants to write to these reserved bits, the user has to read back these
reserved bits (RO or RW) first, then “OR” with the read value of the reserved bits and write back to these reserved bits.
Bit Type Definition
RO = Read only.
WO = Write only.
RW = Read/Write.
W1C = Write 1 to Clear (writing an “1” to clear this bit).
0x00 – 0x05: Reserved
Bus Error Status Register (0x06 – 0x07): BESR
This register flags the different kinds of errors on the host bus.
Chip Configuration Register (0x08 – 0x09): CCR
This register indicates the chip configuration mode based on strapping and bonding options
August 2009
Micrel, Inc.
Bit
15
14-11
10-0
Bit
15-11
10
9
8
7
0
-
-
-
-
-
0
-
Default Value
Default Value
R/W
RO
(W1C)
RO
RO
R/W
RO
RO
RO
RO
RO
Description
IBEC Illegal Byte Enable Combination
1: illegal byte enable combination occurs. The illegal combination value can be
found from bit 14 to bit 11.
0: legal byte enable combination.
Write 1 to clear this bit.
IBECV Illegal Byte Enable Combination Value
Bit 14: byte enable 3.
Bit 13: byte enable 2.
Bit 12: byte enable 1.
Bit 11: byte enable 0.
This value is valid only when bit 15 is set to 1.
Reserved.
Description
Reserved.
Bus Endian mode
The EESK (pin 29) value is latched into this bit druing power-up/reset.
0: Bus in Big Endian mode, 1: Bus in Little Endian mode.
EEPROM presence
The EEEN (pin 26) value is latched into this bit druing power-up/reset.
0: No external EEPROM, 1: Use external EEPROM.
Reserved.
8-Bit data bus width
This bit value is loaded from either EEPROM or EEDI (pin 30, without EEPROM).
0: Not in 8-bit bus mode operation, 1: In 8-bit bus mode operation.
49
KSZ8851-16/32 MQL/MQLI
M9999-083109-2.0

Related parts for KSZ8851-32MQLI