KSZ8851-32MQLI Micrel Inc, KSZ8851-32MQLI Datasheet - Page 8

• Manufacturer Part Number: KSZ8851-32MQLI
• Description: IC CTLR MAC/PHY NON PCI 128PQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8851-32MQLI

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Bus
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 576-3630; KSZ8851-32MQLI

Micrel, Inc.
KSZ8851-16/32 MQL/MQLI
List of Figures
Figure 1. KSZ8851-16/32MQL/MQLI Functional Diagram ..................................................................................................... 1
Figure 2.128-Pin PQFP for 16-Bit ......................................................................................................................................... 10
Figure 3.128-Pin PQFP for 32-Bit ......................................................................................................................................... 16
Figure 4. Typical Straight Cable Connection ....................................................................................................................... 26
Figure 5. Typical Crossover Cable Connection ................................................................................................................... 27
Figure 6. Auto Negotiation and Parallel Operation .............................................................................................................. 28
Figure 7. KSZ8851M 8-Bit, 16-Bit, and 32-Bit Data Bus Connections ................................................................................ 33
Figure 8. Host TX Single Frame in Manual Enqueue Flow Diagram ................................................................................... 36
Figure 9. Host TX Multiple Frames in Auto- Enqueue Flow Diagram .................................................................................. 37
Figure 10. Host RX Single or Multiple Frames in Auto-Dequeue Flow Diagram ................................................................. 39
Figure 11. PHY Port 1 Near-end (Remote) and Host Far-end (Local) Loopback Paths ...................................................... 41
Figure 12. Asynchronous Cycle ........................................................................................................................................... 81
Figure 13. Address Latching Cycle for All Modes ................................................................................................................ 82
Figure 14. Auto Negotiation Timing ..................................................................................................................................... 83
Figure 15. Reset Timing ....................................................................................................................................................... 84
Figure 16. EEPROM Read Cycle Timing Diagram .............................................................................................................. 85
Figure 17. 128-Pin PQFP Package ...................................................................................................................................... 87
August 2009
8
M9999-083109-2.0