KSZ8851-32MQLI Micrel Inc, KSZ8851-32MQLI Datasheet - Page 57

• Manufacturer Part Number: KSZ8851-32MQLI
• Description: IC CTLR MAC/PHY NON PCI 128PQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8851-32MQLI

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Bus
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 576-3630; KSZ8851-32MQLI

Wakeup Frame 3 Byte Mask 2 Register (0x68 – 0x69): WF3BM2
This register contains the next 16 bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the 33rd byte
of the Wake up frame 3. Setting bit 15 selects the 48th byte of the Wake up frame 3.
Wakeup Frame 3 Byte Mask 3 Register (0x6A – 0x6B): WF3BM3
This register contains the last 16 bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the 49th byte
of the Wake up frame 3. Setting bit 15 selects the 64th byte of the Wake up frame 3.
0x6C – 0x6F: Reserved
Transmit Control Register (0x70 – 0x71): TXCR
This register holds control information programmed by the CPU to control the QMU transmit module function.
August 2009
Micrel, Inc.
Bit
15-0
Bit
15-0
Bit
15-0
Bit
15-9
8
7
6
5
4
3
2
-
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Default Value
0
Default Value
0
Default Value
0
Default Value
R/W
RW
R/W
RW
R/W
RW
R/W
RO
RW
RO
RW
RW
RW
RW
RW
Description
WF3BM1
Wake up Frame 3 Byte Mask 1. The next 16 bytes mask covering bytes 17 to 32 of a
Wake up frame 3 pattern.
Description
WF3BM2
Wake up Frame 3 Byte Mask 2. The next 16 bytes mask covering bytes 33 to 48 of a
Wake up frame 3 pattern.
Description
WF3BM3
Wake up Frame 3 Byte Mask 3. The last 16 bytes mask covering bytes 49 to 64 of a
Wake up frame 3 pattern.
Description
Reserved.
TCGICMP Transmit Checksum Generation for ICMP
When this bit is set, The KSZ8851M is enabled to transmit ICMP frame (only for non-
fragment frame) checksum generation.
Reserved.
TCGTCP Transmit Checksum Generation for TCP
When this bit is set, The KSZ8851M is enabled to transmit TCP frame checksum
generation.
TCGIP Transmit Checksum Generation for IP
When this bit is set, The KSZ8851M is enabled to transmit IP header checksum
generation.
FTXQ Flush Transmit Queue
When this bit is set, The transmit queue memory is cleared and TX frame pointer is reset.
Note: Disable the TXE transmit enable bit[0] first before set this bit, then clear this bit to
normal operation.
TXFCE Transmit Flow Control Enable
When this bit is set and the KSZ8851M is in full-duplex mode, flow control is enabled. The
KSZ8851M transmits a PAUSE frame when the Receive Buffer capacity reaches a
threshold level that will cause the buffer to overflow.
When this bit is set and the KSZ8851M is in half-duplex mode, back-pressure flow control
is enabled. When this bit is cleared, no transmit flow control is enabled.
TXPE Transmit Padding Enable
When this bit is set, the KSZ8851M automatically adds a padding field to a packet shorter
than 64 bytes.
Note: Setting this bit requires enabling the add CRC feature (bit1=1) to avoid CRC errors
for the transmit packet.
57
KSZ8851-16/32 MQL/MQLI
M9999-083109-2.0