KSZ8851-32MQLI Micrel Inc, KSZ8851-32MQLI Datasheet - Page 35

• Manufacturer Part Number: KSZ8851-32MQLI
• Description: IC CTLR MAC/PHY NON PCI 128PQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8851-32MQLI

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Bus
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 576-3630; KSZ8851-32MQLI

Driver Routine for Transmit Packet from Host Processor to KSZ8851M
The transmit routine is called by the upper layer to transmit a contiguous block of data through the Ethernet controller. It is
user’s choice to decide how the transmit routine is implemented. If the Ethernet controller encounters an error while
transmitting the frame, it’s the user’s choice to decide whether the driver should attempt to retransmit the same frame or
discard the data. The following Figures 8 and 9 shows the step-by-step for single and multiple transmit packets from host
processor to KSZ8851M.
August 2009
Register Name
[bit](offset)
RXQCR[3](0x82)
TXFDPR[14](0x84)
IER[14][6](0x90)
ISR[15:0](0x92)
TXNTFSR[15:0](0x9E)
Micrel, Inc.
Set bit 3 to start DMA access from host CPU either read (receive frame data) or write (transmit data frame)
Set bit 14 to enable TXQ transmit frame data pointer register increments automatically on accesses to the
data register.
Set bit 14 to enable transmit interrupt in Interrupt Enable Register
Set bit 6 to enable transmit space available interrupt in Interrupt Enable Register.
Write 1 (0xFFFF) to clear all interrupt status bits after interrupt occurred in Interrupt Status Register.
The host CPU is used to program the total amount of TXQ buffer space which is required for next total
transmit frames size in double-word count.
Table 8. Registers Setting for Transmit Function Block
35
Description
KSZ8851-16/32 MQL/MQLI
M9999-083109-2.0