KSZ8851-32MQLI Micrel Inc, KSZ8851-32MQLI Datasheet - Page 88

• Manufacturer Part Number: KSZ8851-32MQLI
• Description: IC CTLR MAC/PHY NON PCI 128PQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8851-32MQLI

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Bus
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 576-3630; KSZ8851-32MQLI

Acronyms and Glossary
BIU
BPDU
CMOS
CRC
Cut-through switch
DA
DMA
EEPROM Electronically Erasable Programmable Read-only Memory
EISA
EMI
FCS
FID
IGMP
IPG
ISI
ISA
Jumbo Packet
MDI
August 2009
Micrel, Inc.
Bus Interface Unit
Bridge Protocol Data Unit
Complementary Metal Oxide Semiconductor
Cyclic Redundancy Check
Destination Address
Direct Memory Access
Extended Industry Standard Architecture
Electro-Magnetic Interference
Frame Check Sequence
Frame or Filter ID
Internet Group Management Protocol
Inter-Packet Gap
Inter-Symbol Interference
Industry Standard Architecture
Medium Dependent Interface
The host interface function that performs code conversion, buffering,
and the like required for communications to and from a network.
A packet containing ports, addresses, etc. to make sure data being
passed through a bridged network arrives at its proper destination.
A common semiconductor manufacturing technique in which positive
and negative types of transistors are combined to form a current gate
that in turn forms an effective means of controlling electrical current
through a chip.
A common technique for detecting data transmission errors. CRC for
Ethernet is 32 bits long.
A switch typically processes received packets by reading in the full
packet (storing), then processing the packet to determine where it
needs to go, then forwarding it. A cut-through switch simply reads in
the first bit of an incoming packet and forwards the packet. Cut-
through switches do not store the packet.
The address to send packets.
A design in which memory on a chip is controlled independently of
the CPU.
A design in which memory on a chip can be erased by exposing it to
an electrical charge.
A bus architecture designed for PCs using 80x86 processors, or an
Intel 80386, 80486 or Pentium microprocessor. EISA buses are 32
bits wide and support multiprocessing.
A naturally occurring phenomena when the electromagnetic field of
one device disrupts, impedes or degrades the electromagnetic field of
another device by coming into proximity with it. In computer
technology, computer devices are susceptible to EMI because
electromagnetic fields are a byproduct of passing electricity through a
wire. Data lines that have not been properly shielded are susceptible
to data corruption by EMI.
See CRC.
Specifies the frame identifier. Alternately is the filter identifier.
The protocol defined by RFC 1112 for IP multicast transmissions.
A time delay between successive data packets mandated by the
network standard for protocol reasons. In Ethernet, the medium has
to be "silent" (i.e., no data transfer) for a short period of time before a
node can consider the network idle and start to transmit. IPG is used
to correct timing differences between a transmitter and receiver.
During the IPG, no data is transferred, and information in the gap can
be discarded or additions inserted without impact on data integrity.
The disruption of transmitted code caused by adjacent pulses
affecting or interfering with each other.
A bus architecture used in the IBM PC/XT and PC/AT.
A packet larger than the standard Ethernet packet (1500 bytes).
Large packet sizes allow for more efficient use of bandwidth, lower
overhead, less processing, etc.
An Ethernet port connection that allows network hubs or switches to
connect to other hubs or switches without a null-modem, or
crossover, cable. MDI provides the standard interface to a particular
media (copper or fiber) and is therefore 'media dependent.'
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KSZ8851-16/32 MQL/MQLI
M9999-083109-2.0