KSZ8851-32MQLI Micrel Inc, KSZ8851-32MQLI Datasheet - Page 51

• Manufacturer Part Number: KSZ8851-32MQLI
• Description: IC CTLR MAC/PHY NON PCI 128PQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8851-32MQLI

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Bus
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 576-3630; KSZ8851-32MQLI

0x16 – 0x1F: Reserved
On-Chip Bus Control Register (0x20 – 0x21): OBCR
This register controls the on-chip bus clock speed for the KSZ8851M. The default of the on-chip bus clock speed is
125MHz. When the external host CPU is running at a higher clock rate, the on-chip bus should be adjusted for the best
performance.
EEPROM Control Register (0x22 – 0x23): EEPCR
To support an external EEPROM, tie the EEPROM Enable (EEEN) pin to High; otherwise, tie it to Low. If an external
EEPROM is not used, the software programs the host MAC address. If an EEPROM is used in the design (EEPROM
Enable pin to High), the chip host MAC address is loaded from the EEPROM immediately after reset. The KSZ8851M
allows the software to access (read and write) the EEPROM directly; that is, the EEPROM access timing can be fully
controlled by the software if the EEPROM Software Access bit is set.
August 2009
Micrel, Inc.
Bit
15-0
Bit
15-7
6
5-3
2
1-0
Bit
15-5
4
3
2-0
-
-
0
-
0
-
0
-
Default Value
Default Value
0x0
Default Value
0x0
R/W
RW
R/W
RW
RW
RW
RW
RW
R/W
RO
RW
RO
RW
Description
MARH MAC Address High
The Most significant word of the MAC address.
Description
Reserved.
Output Pin Drive Strength
Bi-directional or output pad drive strength selection.
0: 8 mA
1: 16 mA
Reserved.
On-Chip Bus Clock Selection
0: 125MHz (default setting is divided by 1, Bit[1:0]=00)
1: NA (reserved)
On-Chip Bus Clock Divider Selection
00: Divided by 1.
01: Divided by 2.
10: Divided by 3.
11: NA (reserved).
For example to contol the bus clock speed as below:
If Bit 2 = 0 and this value is set 00 to select 125MHz.
If Bit 2 = 0 and this value is set 01 to select 62.5MHz.
Description
Reserved.
EESA EEPROM Software Access
1: enable software to access EEPROM through bit 3 to bit 0.
0: disable software to access EEPROM.
EESB EEPROM Status Bit
Data Receive from EEPROM. This bit directly reads the EEDI pin.
EECB EEPROM Control Bits
Bit 2: Data Transmit to EEPROM. This bit directly controls the device’s EEDO pin.
Bit 1: Serial Clock. This bit directly controls the device’s EESK pin.
Bit 0: Chip Select for EEPROM. This bit directly controls the device’s EECS pin.
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KSZ8851-16/32 MQL/MQLI
M9999-083109-2.0