KSZ8851-32MQLI Micrel Inc, KSZ8851-32MQLI Datasheet - Page 63

• Manufacturer Part Number: KSZ8851-32MQLI
• Description: IC CTLR MAC/PHY NON PCI 128PQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8851-32MQLI

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Bus
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 576-3630; KSZ8851-32MQLI

RX Frame Data Pointer Register (0x86 – 0x87): RXFDPR
The value of this register determines the address to be accessed within the RXQ frame buffer. When the Auto Increment
is set, it will automatically increment the RXQ Pointer on read accesses to the data register.
The counter is incremented is by one for every byte access, by two for every word access, and by four for every double
word access.
0x88 – 0x8B: Reserved
RX Duration Timer Threshold Register (0x8C – 0x8D): RXDTTR
This register is used to program the received frame duration timer threshold.
August 2009
Micrel, Inc.
Bit
15
14
13-11
10-0
Bit
15
14
13
12
11
10-0
Bit
15-0
-
0x0
-
-
0x0
-
0x0
0x0
Default Value
0x000
Default Value
0x000
Default Value
0x0000
R/W
RO
RW
RO
RO
R/W
RO
RW
RO
RW
WO
(Read
back
is “0”)
WO
R/W
RW
Description
Reserved.
TXFPAI TX Frame Data Pointer Auto Increment
When this bit is set, the TX Frame data pointer register increments automatically on
accesses to the data register. The increment is by one for every byte access, by two for
every word access, and by four for every doubleword access.
When this bit is reset, the TX frame data pointer is manually controlled by user to access
the TX frame location.
Reserved.
TXFP TX Frame Pointer
TX Frame Pointer index to the Frame Data register for access.
This field reset to next available TX frame location when the TX Frame Data has been
enqueued through the TXQ command register.
Description
Reserved.
RXFPAI RX Frame Pointer Auto Increment
When this bit is set, the RXQ Address register increments automatically on accesses to
the data register. The increment is by one for every byte access, by two for every word
access, and by four for every double word access.
When this bit is reset, the RX frame data pointer is manually controlled by user to access
the RX frame location.
Reserved.
WST Write Sample Time
This bit is used to select the WRN active to write data valid time as shown in Figure 12.
0: WRN active to write data valid sample time is range of 8nS(min) to 16nS(max).
1: WRN active to write data valid sample time is 4nS(max).
EMS Endian Mode Selection
This bit is used to select either Big or Little Endian mode when Endian mode select
strapping pin (29) is NC or tied to GND.
0: is set to Little Endian Mode
1: is set to Big Endian Mode
RXFP RX Frame Pointer
RX Frame data pointer index to the Data register for access.
This pointer value must reset to 0x000 before each DMA operation from the host CPU to
read RXQ frame buffer.
Description
RXDTT Receive Duration Timer Threshold
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KSZ8851-16/32 MQL/MQLI
M9999-083109-2.0