PIC16F88-I/SO Microchip Technology Inc., PIC16F88-I/SO Datasheet - Page 101

• Manufacturer Part Number: PIC16F88-I/SO
• Description: 18 PIN, 7 KB FLASH, 368 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F88-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

11.1
The BRG supports both the Asynchronous and
Synchronous modes of the AUSART. It is a dedicated
8-bit Baud Rate Generator. The SPBRG register
controls the period of a free running 8-bit timer. In Asyn-
chronous mode, bit BRGH (TXSTA<2>) also controls
the baud rate. In Synchronous mode, bit BRGH is
ignored. Table 11-1 shows the formula for computation
of the baud rate for different AUSART modes which
only apply in Master mode (internal clock).
Given the desired baud rate and F
integer value for the SPBRG register can be calculated
using the formula in Table 11-1. From this, the error in
baud rate can be determined.
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the F
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
TABLE 11-1:
TABLE 11-2:
 2005 Microchip Technology Inc.
Legend: X = value in SPBRG (0 to 255)
98h
18h
99h
Legend:
Address
SYNC
0
1
AUSART Baud Rate Generator
(BRG)
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
TXSTA
RCSTA
SPBRG
Name
OSC
(Asynchronous) Baud Rate = F
(Synchronous) Baud Rate = F
/(16(X + 1)) equation can reduce the
BAUD RATE FORMULA
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Baud Rate Generator Register
CSRC
SPEN
Bit 7
BRGH = 0 (Low Speed)
Bit 6
RX9
TX9
OSC
SREN
TXEN
Bit 5
, the nearest
OSC
OSC
CREN
SYNC
Bit 4
/(64(X + 1))
/(4(X + 1))
ADDEN
Bit 3
—
11.1.1
The PIC16F87/88 has an 8 MHz INTRC that can be
used as the system clock, thereby eliminating the need
for external components to provide the clock source.
When the INTRC provides the system clock, the
AUSART module will also use the INTRC as its system
clock.
frequencies that can be used to generate the AUSART
module’s baud rate.
11.1.2
The system clock is used to generate the desired baud
rate; however, when a low-power mode is entered, the
low-power clock source may be operating at a different
frequency than in full power execution. In Sleep mode,
no clocks are present. This may require the value in
SPBRG to be adjusted.
11.1.3
The data on the RB2/SDO/RX/DT pin is sampled three
times by a majority detect circuit to determine if a high
or a low level is present at the RX pin.
BRGH
FERR
Bit 2
Table 11-1 shows
AUSART AND INTRC OPERATION
LOW-POWER MODE OPERATION
SAMPLING
OERR
TRMT
Baud Rate = F
Bit 1
BRGH = 1 (High Speed)
RX9D
TX9D
PIC16F87/88
Bit 0
N/A
OSC
0000 -010
0000 000x
0000 0000
POR, BOR
some
Value on:
/(16(X + 1))
DS30487C-page 99
of
the INTRC
0000 -010
0000 000x
0000 0000
Value on
all other
Resets