PIC16F88-I/SO Microchip Technology Inc., PIC16F88-I/SO Datasheet - Page 86

• Manufacturer Part Number: PIC16F88-I/SO
• Description: 18 PIN, 7 KB FLASH, 368 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F88-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F87/88
9.3
In Pulse-Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTB data latch,
the TRISB<x> bit must be cleared to make the CCP1
pin an output.
Figure 9-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 9.3.3 “Setup
for PWM Operation”.
FIGURE 9-3:
A PWM output (Figure 9-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 9-4:
DS30487C-page 84
CCPR1H (Slave)
Note:
Note 1: 8-bit timer is concatenated with 2-bit internal Q
Duty Cycle Registers
Comparator
CCPR1L
TMR2 = PR2
TMR2
PR2
Comparator
PWM Mode
Duty Cycle
clock, or 2 bits of the prescaler, to create 10-bit
time base.
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTB I/O data
latch.
Period
(Note 1)
Clear Timer,
CCP1 pin and
latch D.C.
TMR2 = Duty Cycle
SIMPLIFIED PWM BLOCK
DIAGRAM
PWM OUTPUT
TMR2 = PR2
CCP1CON<5:4>
R
S
Q
TRISB<x>
CCP1 pin
9.3.1
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula.
EQUATION 9-1:
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
• The PWM duty cycle is latched from CCPR1L into
9.3.2
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> bits contain
the two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time.
EQUATION 9-2:
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch
are used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
cycle = 0%, the CCP1 pin will not be set)
CCPR1H
Note:
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
PWM Period = [(PR2) + 1] • 4 • T
The Timer2 postscaler (see Section 8.0
“Timer2 Module”) is not used in the deter-
mination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
PWM PERIOD
PWM DUTY CYCLE
T
(TMR2 Prescale Value)
OSC
 2005 Microchip Technology Inc.
• (TMR2 Prescale Value)
OSC
•