PIC16F88-I/SO Microchip Technology Inc., PIC16F88-I/SO Datasheet - Page 18

• Manufacturer Part Number: PIC16F88-I/SO
• Description: 18 PIN, 7 KB FLASH, 368 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F88-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F87/88
TABLE 2-1:
DS30487C-page 16
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
Legend:
Note 1:
Address
Bank 2
Bank 3
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1,2)
(1,2)
(2)
(2)
2:
3:
4:
INDF
TMR0
PCL
STATUS
FSR
WDTCON
PORTB
PCLATH
INTCON
EEDATA
EEADR
EEDATH
EEADRH
INDF
OPTION_REG
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
EECON1
EECON2
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
These registers can be addressed from any bank.
RA5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
PIC16F88 device only.
Name
—
—
—
—
—
—
—
—
—
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
PORTB Data Latch when written; PORTB pins when read (PIC16F87)
PORTB Data Latch when written; PORTB pins when read (PIC16F88)
Unimplemented
Unimplemented
Unimplemented
EEPROM/Flash Data Register Low Byte
EEPROM/Flash Address Register Low Byte
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
PORTB Data Direction Register
Unimplemented
Unimplemented
Unimplemented
EEPROM Control Register 2 (not a physical register)
Reserved, maintain clear
Reserved, maintain clear
EEPGD
RBPU
Bit 7
GIE
IRP
GIE
IRP
—
—
—
—
—
INTEDG
PEIE
PEIE
Bit 6
RP1
RP1
—
—
—
—
—
—
EEPROM/Flash Data Register High Byte
TMR0IE
TMR0IE
T0CS
Bit 5
RP0
RP0
—
—
—
—
—
Write Buffer for the Upper 5 bits of the Program Counter
Write Buffer for the Upper 5 bits of the Program Counter
WDTPS3
INT0IE
INT0IE
FREE
T0SE
Bit 4
TO
TO
—
EEPROM/Flash Address Register High Byte
WDTPS2
WRERR
RBIE
RBIE
Bit 3
PSA
PD
PD
WDTPS1
TMR0IF
TMR0IF
WREN
Bit 2
PS2
Z
Z
WDTPS0
INT0IF
INT0IF
Bit 1
PS1
WR
DC
DC
 2005 Microchip Technology Inc.
SWDTEN
RBIF
RBIF
Bit 0
PS0
RD
C
C
0000 0000
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
---0 1000
xxxx xxxx
00xx xxxx
---0 0000
0000 000x
xxxx xxxx
xxxx xxxx
--xx xxxx
---- xxxx
0000 0000
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
1111 1111
---0 0000
0000 000x
x--x x000
---- ----
0000 0000
0000 0000
POR, BOR
Value on:
—
—
—
—
—
—
—
Details
26, 135
19, 69,
19, 69,
18, 69
58, 83
28, 34
page
135
135
142
135
135
135
135
135
on
69
17
58
77
34
34
34
34
17
77
34
—
—
—
—
—
—
—
—
—