PIC16F88-I/SO Microchip Technology Inc., PIC16F88-I/SO Datasheet - Page 45

• Manufacturer Part Number: PIC16F88-I/SO
• Description: 18 PIN, 7 KB FLASH, 368 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F88-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

4.7
4.7.1
When SCS bits are configured to run from the INTRC,
a clock transition is generated if the system clock is
not already using the INTRC. The event will clear the
OSTS bit, switch the system clock from the primary
system clock (if SCS<1:0> = 00) determined by the
value contained in the configuration bits, or from the
T1OSC (if SCS<1:0> = 01) to the INTRC clock option
and shut down the primary system clock to conserve
power. Clock switching will not occur if the primary
system clock is already configured as INTRC.
FIGURE 4-7:
 2005 Microchip Technology Inc.
Note 1:
SCS<1:0>
Program
INTOSC
Counter
System
OSC1
Clock
2:
3:
4:
Power-Managed Modes
T
T
T
T
Q1
OSC
SCS
INP
DLY
RC_RUN MODE
T
Q2
OSC (2)
= 32 s typical.
= 50 ns minimum.
= 8 T
= 1 T
PC
Q3
INP
INP
Q4
.
.
TIMING DIAGRAM FOR XT, HS, LP, EC AND EXTRC TO RC_RUN MODE
Q1
T
DLY
(4)
T
INP
(1)
T
SCS (3)
PC + 1
If the system clock does not come from the INTRC
(31.25 kHz) when the SCS bits are changed and the
IRCF bits in the OSCCON register are configured for a
frequency other than INTRC, the frequency may not be
stable immediately. The IOFS bit (OSCCON<2>) will
be set when the INTOSC or postscaler frequency is
stable, after 4 ms (approx.).
After a clock switch has been executed, the OSTS bit
is cleared, indicating a low-power mode and the
device does not run from the primary system clock.
The internal Q clocks are held in the Q1 state until
eight falling edge clocks are counted on the INTRC
oscillator.
transpired, the clock input to the Q clocks is released
and operation resumes (see Figure 4-7).
Q1
Q2
After
Q3
the
Q4
PIC16F87/88
eight
Q1
clock
Q2
PC + 2
DS30487C-page 43
Q3
periods
Q4
PC + 3
Q1
have