PIC16F88-I/SO Microchip Technology Inc., PIC16F88-I/SO Datasheet - Page 142

• Manufacturer Part Number: PIC16F88-I/SO
• Description: 18 PIN, 7 KB FLASH, 368 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F88-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F87/88
15.10.1
External interrupt on the RB0/INT pin is edge-triggered,
either rising if bit INTEDG (OPTION_REG<6>) is set,
or falling if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit, INT0IF
(INTCON<1>), is set. This interrupt can be disabled by
clearing enable bit INT0IE (INTCON<4>). Flag bit
INT0IF must be cleared in software in the Interrupt
Service Routine before re-enabling this interrupt. The
INT interrupt can wake-up the processor from Sleep, if
bit INT0IE was set prior to going into Sleep. The status
of global interrupt enable bit GIE decides whether or
not the processor branches to the interrupt vector,
following wake-up. See Section 15.13 “Power-Down
Mode (Sleep)” for details on Sleep mode.
15.10.2
An overflow (FFh
flag bit TMR0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit TMR0IE
(INTCON<5>), see Section 6.0 “Timer0 Module”.
EXAMPLE 15-1:
DS30487C-page 140
MOVWF
SWAPF
CLRF
MOVWF
MOVF
MOVWF
CLRF
:
:(ISR)
:
MOVF
MOVWF
SWAPF
MOVWF
SWAPF
SWAPF
INT INTERRUPT
TMR0 INTERRUPT
W_TEMP
STATUS, W
STATUS
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
PCLATH_TEMP, W
PCLATH
STATUS_TEMP, W
STATUS
W_TEMP, F
W_TEMP, W
00h) in the TMR0 register will set
SAVING STATUS, W AND PCLATH REGISTERS IN RAM
;Copy W to TEMP register
;Swap status to be saved into W
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
;Save status to bank zero STATUS_TEMP register
;Only required if using page 1
;Save PCLATH into W
;Page zero, regardless of current page
;(Insert user code here)
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
15.10.3
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>), see
Section 3.2 “EECON1 and EECON2 Registers”.
15.11 Context Saving During Interrupts
During an interrupt, only the return PC value is saved on
the stack. Typically, users may wish to save key registers
during an interrupt (i.e., W, STATUS registers).
Since the upper 16 bytes of each bank are common in
the PIC16F87/88 devices, temporary holding registers
W_TEMP,
should be placed in here. These 16 locations don’t
require banking and therefore, make it easier for
context save and restore. The same code shown in
Example 15-1 can be used.
PORTB INTCON CHANGE
STATUS_TEMP
 2005 Microchip Technology Inc.
and
PCLATH_TEMP