PIC16F88-I/SO Microchip Technology Inc., PIC16F88-I/SO Datasheet - Page 17

• Manufacturer Part Number: PIC16F88-I/SO
• Description: 18 PIN, 7 KB FLASH, 368 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F88-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 2-1:
 2005 Microchip Technology Inc.
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:
Note 1:
Address
Bank 1
(2)
(2)
(2)
(2)
(1,2)
(2)
2:
3:
4:
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIE1
PIE2
PCON
OSCCON
OSCTUNE
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
ANSEL
CMCON
CVRCON
ADRESL
ADCON1
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
These registers can be addressed from any bank.
RA5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
PIC16F88 device only.
Name
—
—
—
—
—
—
—
—
(4)
(4)
(4)
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address Pointer
PORTB Data Direction Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Timer2 Period Register
Synchronous Serial Port (I
Unimplemented
Unimplemented
Unimplemented
Baud Rate Generator Register
Unimplemented
A/D Result Register Low Byte
CVREN
TRISA7
C2OUT
OSFIE
RBPU
CSRC
ADFM
Bit 7
SMP
GIE
IRP
—
—
—
—
—
—
INTEDG
CVROE
TRISA6
ADIE
C1OUT
ADCS2
IRCF2
ANS6
CMIE
PEIE
Bit 6
CKE
RP1
TX9
—
—
—
(4)
TRISA5
TMR0IE
VCFG1
C2INV
IRCF1
CVRR
T0CS
TUN5
2
TXEN
ANS5
RCIE
Bit 5
RP0
C™ mode) Address Register
D/A
—
—
—
(3)
PORTA Data Direction Register (TRISA<4:0>)
Write Buffer for the Upper 5 bits of the Program Counter
VCFG0
INT0IE
C1INV
IRCF0
SYNC
TUN4
ANS4
T0SE
EEIE
Bit 4
TXIE
TO
—
—
P
SSPIE
OSTS
TUN3
ANS3
CVR3
RBIE
Bit 3
PSA
CIS
PD
—
—
—
—
S
TMR0IF
CCP1IE
BRGH
TUN2
ANS2
CVR2
IOFS
Bit 2
CM2
PS2
R/W
—
—
—
Z
TMR2IE
INT0IF
TRMT
SCS1
TUN1
ANS1
CVR1
Bit 1
POR
CM1
PS1
DC
UA
—
—
PIC16F87/88
TMR1IE
CVR0
SCS0
TUN0
TX9D
ANS0
RBIF
BOR
Bit 0
CM0
PS0
BF
—
—
C
DS30487C-page 15
0000 0000
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
1111 1111
1111 1111
---0 0000
0000 000x
-000 0000
00-0 ----
---- --0q
-000 0000
--00 0000
1111 1111
0000 0000
0000 0000
0000 -010
0000 0000
-111 1111
0000 0111
000- 0000 126, 128
xxxx xxxx
0000 ----
POR, BOR
Value on:
—
—
—
—
—
—
—
—
126, 128
52, 115,
26, 135
52, 126
99, 103
Details
19, 69,
18, 69
58, 85
20, 80
22, 34
80, 85
88, 95
97, 99
page
121,
135
135
135
120
120
120
on
17
—
—
—
77
24
40
38
95
—
—
—
—
—