TE28F640J3D75 Intel, TE28F640J3D75 Datasheet - Page 20

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TE28F640J3D75

Manufacturer Part Number
TE28F640J3D75
Description
Manufacturer
Intel
Datasheet

Specifications of TE28F640J3D75

Cell Type
NOR
Density
64Mb
Access Time (max)
75ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
23/22Bit
Operating Supply Voltage (typ)
3/3.3V
Sync/async
Asynchronous
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
8M/4Mword
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Not Compliant
5.3.1
Table 6:
Note:
5.3.2
5.4
Datasheet
20
Power Supply
V
V
Voltage
V
CCQ(min)
PEN(min)
CC(min)
Power-Up/Down Sequence
Power-Up/Down Characteristics
To prevent conditions that could result in spurious program or erase operations, the
power-up/power-down sequence shown in here is recommended. Note that each power
supply must reach its minimum voltage range before applying/removing the next
supply voltage.
† Power supplies connected or sequenced together.
Device inputs must not be driven until all supply voltages reach their minimum range.
RP# should be low during power transitions.
Power Supply Decoupling
When the device is enabled, many internal conditions change. Circuits are energized,
charge pumps are switched on, and internal voltage nodes are ramped. All of this
internal activities produce transient signals. The magnitude of the transient signals
depends on the device and system loading. To minimize the effect of these transient
signals, a 0.1 µF ceramic capacitor is required across each VCC/VSS and VCCQ signal.
Capacitors should be placed as close as possible to device connections.
Additionally, for every eight flash devices, a 4.7 µF electrolytic capacitor should be
placed between VCC and VSS at the power supply connection. This 4.7 µF capacitor
should help overcome voltage slumps caused by PCB (printed circuit board) trace
inductance.
Reset
By holding the flash device in reset during power-up and power-down transitions,
invalid bus conditions may be masked. The flash device enters reset mode when RP# is
driven low. In reset, internal flash circuitry is disabled and outputs are placed in a high-
impedance state. After return from reset, a certain amount of time is required before
the flash device is able to perform normal operations. After return from reset, the flash
device defaults to asynchronous page mode. If RP# is driven low during a program or
erase operation, the program or erase operation will be aborted and the memory
contents at the aborted block or address are no longer valid. See
Waveform for Reset Operation” on page 29
timings.
2nd
3rd
1st
2nd
Power-UpSequence
1st
1st
2nd
Sequencing not
required
for detailed information regarding reset
Numonyx™ Embedded Flash Memory (J3 v. D)
2nd
3rd
1st
Power-Down Sequence
1st
2nd
Figure 16, “AC
2nd
1st
Sequencing not
November 2007
required
308551-05

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