TE28F640J3D75 Intel, TE28F640J3D75 Datasheet - Page 45

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TE28F640J3D75

Manufacturer Part Number
TE28F640J3D75
Description
Manufacturer
Intel
Datasheet

Specifications of TE28F640J3D75

Cell Type
NOR
Density
64Mb
Access Time (max)
75ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
23/22Bit
Operating Supply Voltage (typ)
3/3.3V
Sync/async
Asynchronous
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
8M/4Mword
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Not Compliant
Numonyx™ Embedded Flash Memory (J3 v. D)
9.7.6
Figure 20: Protection Register Memory Map
Note:
Table 28: Word-Wide Protection Register Addressing
November 2007
308551-05
Note:
LOCK
Word
A0 is not used in x16 mode when accessing the protection register map. See
is used, see
0
1
2
3
4
5
6
7
All address lines not specified in the above table must be 0 when accessing the Protection Register (i.e., A[MAX:9] = 0.)
Locking the OTP Protection Register
The user-programmable segment of the Protection Register is lockable by programming
Bit 1 of the Protection Lock Register (PLR) to 0. Bit 0 of this location is programmed to
0 at the Numonyx factory to protect the unique device number. Bit 1 is set using the
Protection Program command to program “0xFFFD” to the PLR. After these bits have
been programmed, no further changes can be made to the values stored in the
Protection Register. Protection Program commands to a locked section will result in a
Status Register error (SR.4 and SR.1 will be set). PR lockout state is not reversible.
Table 29
Factory
Factory
Factory
Factory
User
User
User
User
Both
Use
for x8 addressing.
Address
Word
0x88
0x85
0x84
0x81
0x80
A8
1
1
1
1
1
1
1
1
1
15 14 13 12 11 10 9
128-Bit Protection Register 0
A[24:1]: 256 Mbit
A[23:1]: 128 Mbit
(Factory-Programmed)
(User-Programmable)
A7
0
0
0
0
0
0
0
0
0
64-bit Segment
64-bit Segment
Lock Register 0
8
7
A6
0
0
0
0
0
0
0
0
0
6
5
4
3
A[22:1]: 64 Mbit
A[21:1]: 32 Mbit
A5
2
0
0
0
0
0
0
0
0
0
1
0
Table 28
A4
0
0
0
0
0
0
0
0
1
for x16 addressing. If x8 mode A0
A3
0
0
0
0
1
1
1
1
0
A2
0
0
1
1
0
0
1
1
0
Datasheet
A1
0
1
0
1
0
1
0
1
0
45

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