TE28F640J3D75 Intel, TE28F640J3D75 Datasheet - Page 23

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TE28F640J3D75

Manufacturer Part Number
TE28F640J3D75
Description
Manufacturer
Intel
Datasheet

Specifications of TE28F640J3D75

Cell Type
NOR
Density
64Mb
Access Time (max)
75ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
23/22Bit
Operating Supply Voltage (typ)
3/3.3V
Sync/async
Asynchronous
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
8M/4Mword
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Not Compliant
Numonyx™ Embedded Flash Memory (J3 v. D)
7.0
Figure 9:
Figure 10: Timing Signal Name Decoder
Note:
7.1
Table 10: Read Operations (Sheet 1 of 2)
November 2007
308551-05
Address
Data - Read
Data - Write
Chip Enable (CE#)
Output Enable (OE#)
Write Enable (WE#)
Address Valid (ADV#)
Reset (RST#)
Clock (CLK)
WAIT
R1
#
t
AVAV
Sym
Signal
Timing Signal Naming Convention
AC Characteristics
Timing symbols used in the timing diagrams within this document conform to the
following convention:
Exceptions to this convention include tACC and tAPA. tACC is a generic timing symbol
that refers to the aggregate initial-access delay as determined by tAVQV, tELQV, and
tGLQV (whichever is satisfied last) of the flash device. tAPA is specified in the flash
device’s data sheet, and is the address-to-data delay for subsequent page-mode reads.
Read Specifications
Asynchronous Specifications V
Read/Write Cycle Time
Source Signal
Source State
A
Q
D
E
G
W
V
P
C
T
Parameter
t
Code
E
CC
= 2.7 V–3.6 V
L Q V
High
Low
High-Z
Low-Z
Valid
Invalid
128 Mbit
256 Mbit
Density
32 Mbit
64 Mbit
(3)
and V
State
Target State
Target Signal
Min
75
75
75
95
CCQ
= 2.7 V–3.6 V
Max
(3)
H
L
Z
X
V
I
Unit
ns
Code
Notes
1,2
1,2
1,2
1,2
Datasheet
23

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