TE28F640J3D75 Intel, TE28F640J3D75 Datasheet - Page 40

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TE28F640J3D75

Manufacturer Part Number
TE28F640J3D75
Description
Manufacturer
Intel
Datasheet

Specifications of TE28F640J3D75

Cell Type
NOR
Density
64Mb
Access Time (max)
75ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
23/22Bit
Operating Supply Voltage (typ)
3/3.3V
Sync/async
Asynchronous
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
8M/4Mword
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Not Compliant
Note:
9.4
Table 22: Block-Erase Command Bus-Cycle
Note:
Note:
Datasheet
40
Block Erase
After issuing the confirm command, write-buffer contents are programmed into the
flash memory array. The Status Register indicates a busy status (SR7 = 0) during array
programming.Issuing the Read Array command to the device while it is actively
programming or erasing causes subsequent reads from the device to output invalid
data. Valid array data is output only after the program or erase operation has finished.
Upon completion of array programming, the Status Register indicates ready (SR7 = 1).
A full Status Register check should be performed to check for any programming errors,
then cleared by using the Clear Status Register command.
Additional buffered programming operations can be initiated by issuing another setup
command, and repeating the buffered programming bus-cycle sequence. However, any
errors in the Status Register must first be cleared before another buffered
programming operation can be initiated.
Block Erase Operations
Erasing a block changes ‘zeros’ to ‘ones’. To change ones to zeros, a program operation must be performed
(see
entire block is erased each time an erase command sequence is issued. Once a block is
fully erased, all addressable locations within that block read as logical ones (FFFFh).
Only one block-erase operation can occur at a time, and is not permitted during a program suspend.
To perform a block-erase operation, issue the Block Erase command sequence at the
desired block address.
the two-cycle Block Erase command sequence.
In case of 256 Mb device (2x128), the command should be issued to the base address of the die
A block-erase operation requires the addressed block to be unlocked, and a valid
voltage applied to VPEN throughout the block-erase operation. Otherwise, the
operation will abort, setting the appropriate Status Register error bit(s).
The Erase Confirm command latches the address of the block to be erased. The
addressed block is preconditioned (programmed to all zeros), erased, and then verified.
The read mode of the device is automatically changed to Read Status Register mode,
and remains in effect until another read-mode command is issued.
During a block-erase operation, STS and the Status Register indicates a busy status
(SR7 = 0). Upon completion, STS and the Status Register indicates a ready status (SR7
= 1). The Status Register should be checked for any errors, then cleared. If any errors
did occur, subsequent erase commands to the device are ignored unless the Status
Register is cleared.
The only valid commands during a block erase operation are Read Array, Read Device
Information, CFI Query, and Erase Suspend. After the block-erase operation has
completed, any valid command can be issued.
Issuing the Read Array command to the device while it is actively erasing causes
subsequent reads from the device to output invalid data. Valid array data is output only
after the block-erase operation has finished.
Command
Section 9.3, “Programming
Table 22, “Block-Erase Command Bus-Cycle” on page 40
Operations”). Erasing is performed on a block basis - an
Device Address
Address Bus
Setup Write Cycle
Numonyx™ Embedded Flash Memory (J3 v. D)
Data Bus
0020h
Address Bus
Block Address
Confirm Write Cycle
November 2007
Data Bus
308551-05
00D0h
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