DS80C400 Maxim, DS80C400 Datasheet - Page 14

no-image

DS80C400

Manufacturer Part Number
DS80C400
Description
The DS80C400 network microcontroller offers the highest integration available in an 8051 device
Manufacturer
Maxim
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS80C400
Manufacturer:
DALLAS
Quantity:
748
Part Number:
DS80C400-FNY
Manufacturer:
DALLAS
Quantity:
85
Part Number:
DS80C400-FNY
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS80C400-FNY+
Manufacturer:
TDK-Lambda
Quantity:
34
Part Number:
DS80C400-FNY+
Manufacturer:
Maxim
Quantity:
3 861
Part Number:
DS80C400-FNY+
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS80C400-FNY+
Manufacturer:
MAXI/DALLAS
Quantity:
20 000
MOVX CHARACTERISTICS (NONMULTIPLEXED ADDRESS/DATA BUS) (Note 1)
(V
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
Note 2: All parameters apply to both commercial and industrial temperature operation unless otherwise noted.
Note 3: CST is the stretch cycle value as determined by the MD2, MD1, and MD0 bits of the CKCON register. t
Note 4: All signals characterized with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN, RD, and WR with 100pF. The following
Note 5: References to the XTAL or CLK signal in timing diagrams is to assist in determining the relative occurrence of events, not for determing
Input Instruction Float After PSEN
PSEN High to Data Address, Port 4 CE,
Port 5 PCE Valid
RD Pulse Width (P3.7 or PSEN)
WR Pulse Width (P3.6)
RD (P3.7 or PSEN) Low to Valid Data In
Data Hold After RD (P3.7 or PSEN) High
Data Float After RD (P3.7 or PSEN) High
PSEN High to WR Low
PSEN High to (RD or PSEN) Low
Port 7 Address to Valid Data In
Port 2, 4, 6 Address, Port 4 CE or Port 5
PCE to Valid Data In
Port 7 Address to (RD or PSEN) or WR
Low
Port 2, 4, 6 Address, Port 4 CE or Port 5
PCE to (RD or PSEN) or WR Low
Data Valid to WR Transition
Data Hold After WR High
(RD or PSEN) or WR High to Port 4 CE
or Port 5 PCE High
CC3
= 3.0V to 3.6V, V
associated with the internal system clock and are related to the external clock. See the System Clock Time Periods table.
signals, when configured for memory interface, are also characterized with 100pF loading: Port 4 (CE0-3, A16–A19), Port 5.4–5.7
(PCE0-3), Port 6.0–6.5 (CE4-7, A20, A2), Port 7 (demultiplexed mode A0–A7).
absolute signal timing with respect to the external clock.
PARAMETER
CC1
= 1.8V +±10%, T
SYMBOL
t
t
t
t
t
t
t
t
WHCEH
t
t
t
t
t
t
t
WLWH
AVDV1
AVDV2
AVWL1
AVWL2
t
WHQX
PHWL
QVWX
PHAV
RLRH
RHDX
RHDZ
RLDV
PHRL
PXIZ
A
= -40°C to +85°C.)
10t
(4 x C
(4 x C
2t
5t
t
t
CLCL
CLCL
14 of 97
CLCL
CLCL
CLCL
11t
11t
10t
2t
2t
2t
3t
2t
3t
2t
6t
2
t
t
t
t
CHCL
CHCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
ST
+ t
+ t
ST
MIN
CLCL
CLCL
CLCL
+ t
+ t
+ t
-2
) t
0
)t
CLCH
CHCL
CLCH
CHCL
CLCL
- 5
- 4
- 3
- 5
CLCL
CLCH
- 7
- 5
- 5
- 3
- 3
- 3
- 3
- 5
- 7
- 3
- 3
- 5
- 5
- 5
- 5
- 3
-5
- 3
- 5
(4 x C
(4 x C
(4 x C
(4 x C
(4 x C
3t
5t
t
CLCL
CLCL
CLCL
11t
2t
3t
t
t
t
2t
3t
2t
6t
ST
CHCL
CLCH
ST
CLCH
t
ST
ST
CLCL
CLCL
CLCL
+ t
ST
CLCL
CLCL
CLCL
CLCL
MAX
+ t
+ t
CLCL
+ 2)t
+ 10)t
+ 10)t
19
)t
+ 2)t
CHCL
CLCH
CHCL
CLCL
+ 13
- 19
- 19
- 17
- 5
- 19
- 5
- 5
- 5
- 5
- 5
CLCL
CLCL
CLCL
+12
CLCL
- 19
- 17
+12
- 19
+
+
-
CLCL
UNITS
, t
CLCH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
, t
CHCL
are time periods
C
4 ≤ C
1 ≤ C
1 ≤ C
1 ≤ C
4 ≤ C
4 ≤ C
4 ≤ C
4 ≤ C
4 ≤ C
1 ≤ C
4 ≤ C
1 ≤ C
4 ≤ C
1 ≤ C
4 ≤ C
1 ≤ C
4 ≤ C
STRETCH
1≤ C
1≤ C
1≤ C
1≤ C
1≤ C
1≤ C
ST
VALUES
C
C
C
C
C
C
C
C
C
C
C
C
C
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
(MD2:0)
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= 0
=0
=0
≤ 3
≤ 3
≤ 3
≤ 3
≤ 3
≤ 3
≤ 7
≤ 7
≤ 7
≤ 7
≤ 7
≤ 7
≤ 7
≤ 7
≤ 7
≤ 3
≤ 7
≤ 3
≤ 7
≤ 3
≤ 7
≤ 3
≤ 7

Related parts for DS80C400