DS80C400 Maxim, DS80C400 Datasheet - Page 64

• Manufacturer Part Number: DS80C400
• Description: The DS80C400 network microcontroller offers the highest integration available in an 8051 device
• Manufacturer: Maxim

Transmit/Receive Packet Buffer Memory (8kB)
The DS80C400 Ethernet controller uses 8kB of internal SRAM as transmit/receive packet buffer memory. This
SRAM is read/write accessible as data memory by the CPU using the MOVX instruction. The BCU also has access
to this SRAM, and automatically writes/reads packet buffer memory whenever it needs to store or retrieve Ethernet
packet information. The logical MOVX address range of the 8kB SRAM is determined by the IDM1:0 bits of the
MCON (C6h) SFR.
When used for Ethernet packet buffer memory, the 8kB SRAM is logically configured into (32) pages of 64 words
each, where a word consists of 4 Bytes. These 32 pages can be dynamically allocated between Ethernet transmit
and receive buffer memory. The five least significant bits of the Ethernet buffer size (EBS; E5h) SFR specify how
many pages are allocated for receive buffer memory. The remaining pages of the 32 are used as transmit buffer
memory. Note that transmit and receive data packets can span multiple pages. The reset default state of the
Ethernet buffer size select bits (EBS.4–EBS.0) is 00000b, which configures all 32 pages as transmit buffer
memory. As an example, setting EBS.4–EBS.0 = 10000b would result in pages 0–15 (16 pages) being configured
as receive buffer memory and pages 16–31 (16 pages) being configured as transmit buffer memory. A setting of
11111b leaves a single page (page 31) for transmit buffer memory and configures pages 0–30 (31 pages) as
receive buffer memory. Changing the transmit/receive buffer-size settings flush the contents of the receive buffer
and the receive FIFO.
Table 16. Packet Buffer Memory Location
Figure 10. Transmit/Receive Data Buffer Memory
(EBS.4–EBS.0)
BUFFER SIZE
(MCON.7, MCON.6)
SETTING
(32 - n PAGES)
TRANSMIT
(n PAGES)
BUFFER
RECEIVE
BUFFER
IDM1:0
00
01
10
11
Table 16
Figure 10
8kB INTERNAL SRAM
(ETHERNET PACKET BUFFER MEMORY)
shows the available address range settings.
INTERNAL 8kB SRAM LOCATION
PAGE (n - 2)
PAGE (n - 1)
is an illustration of the 8kB buffer memory map and addressing scheme.
PAGE 31
PAGE 0
PAGE 1
PAGE n
.
.
.
.
.
.
.
.
.
FFE000h–FFFFFFh
00E000h–00FFFFh
000000h–001FFFh
Reserved
64 of 97
(Per IDM1:0)
xxxxxxxx xxx
BUFFER MEMORY ADDRESS (24-Bit)
EXAMPLE: PAGE 1, WORD 2, BYTE 3
STATUS WORD (WORD 0)
DS80C400 Network Microcontroller
WORD 63
WORD 2
PAGE 1
WORD 1
PAGE
00001
.
.
.
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WORD
000010
BYTE
11