DS80C400 Maxim, DS80C400 Datasheet - Page 91

• Manufacturer Part Number: DS80C400
• Description: The DS80C400 network microcontroller offers the highest integration available in an 8051 device
• Manufacturer: Maxim

Note that the computation of the Internet checksum over the message data and 16-bit checksum field should yield
0000h.
Clock Control and Power Management
The DS80C400 includes a number of unique features that allow flexibility in selecting system clock sources and
operating frequencies. To support the use of inexpensive crystals while allowing full speed operation, a clock
multiplier is included in the microcontroller’s clock circuit. Also, in addition to the standard 80C32 idle and power-
down (stop) modes, the DS80C400 provides a PMM. This mode allows the microcontroller to continue instruction
execution at a very low speed to significantly reduce power consumption (below even idle mode). The DS80C400
also features several enhancements to stop mode that make this extremely low-power mode more useful. Each of
these features is discussed in detail below.
System Clock Control
As mentioned previously, the microcontroller contains special clock-control circuitry that simultaneously provides
maximum timing flexibility and maximum availability and economy in crystal selection. The logical operation of the
system clock divide control function is shown in
selects one of three sources for the internal system clock:
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The system clock control circuitry generates two clock signals that are used by the microcontroller. The internal
system clock provides the time base for timers and internal peripherals. The system clock is run through a divide-
by-4 circuit to generate the machine cycle clock that provides the time base for CPU operations. All instructions
execute in one to five machine cycles. It is important to note the distinction between these two clock signals, as
they are sometimes confused, creating errors in timing calculations.
Setting CTM = 1 and CD1, CD0 = 00b enables the frequency multiplier, either doubling or quadrupling the
frequency of the crystal oscillator or external clock source. The 4X/2X bit controls the multiplying factor, selecting
twice or four times the frequency when set to 0 or 1, respectively. Enabling the frequency multiplier results in
apparent instruction execution speeds of 2 or 1 clocks. Regardless of the configuration of the frequency multiplier,
the system clock of the microcontroller can never be operated faster than 75MHz. This means that the maximum
external clock source is 18.75MHz when using the 4X setting, and 37.5MHz when using the 2X setting.
The primary advantage of the clock multiplier is that it allows the microcontroller to use slower crystals to achieve
the same performance level. This reduces EMI and cost, as slower crystals are generally more available and thus
less expensive.
Setting CD1, CD0 = 11b enables the PMM. When placed into PMM, the incoming crystal or clock frequency is
divided by 256, resulting in a machine cycle of 1024 clocks. Note that power consumption in PMM is less than idle
mode. While both modes leave the power-hungry internal timers running, PMM runs all clocked functions such as
timers at the rate of crystal divided by 1024, rather than crystal divided by 4. Even though instruction execution
continues in PMM (albeit at a reduced speed), it still consumes less power than idle mode. As a result, there is little
reason to use idle mode in new designs.
The system clock and machine cycle rate changes one machine cycle after the instruction changing the control
bits. Note that the change affects all aspects of system operation, including timers and baud rates. Using the
switchback feature, described later, can eliminate many of the problems associated with the PMM.
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Crystal oscillator or external clock source
(Crystal oscillator or external clock source) divided by 256
(Crystal oscillator or external clock source) frequency multiplied by 2 or 4 times
Repeat steps 2, 3 over the message data for which the checksum is to be computed
Read MSB of 16-bit value from OCAD
One’s complement of the byte last read is the Internet checksum MSB
Read LSB of 16-bit value from OCAD
One’s complement of the byte last read is the Internet checksum LSB
Figure
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20. A 3:1 multiplexer, controlled by CD1, CD0 (PMR.7-6),