DS80C400 Maxim, DS80C400 Datasheet - Page 52

• Manufacturer Part Number: DS80C400
• Description: The DS80C400 network microcontroller offers the highest integration available in an 8051 device
• Manufacturer: Maxim

Each CSR register is documented as follows:
CSR Register:
Register Address:
Bit Names:
Reset State:
RA, Receive All. This bit overrides the flush-filter failed-packet function if that function has been enabled
(EBS.7 = 1).
0 = default frame handling (default)
1 = all error-free frames are received with packet filter bit set (= 1) in the receive status word
BLE, Big-/Little-Endian Mode
0 = data buffers are operated in little-endian mode (default)
1 = data buffers are operated in big-endian mode
HBD, Heart-Beat Disable. This bit is only useful in ENDEC mode and has no effect on MII mode operation.
0 = heart-beat signal quality-generator function enabled (default)
1 = heart-beat signal quality-generator function is disabled
PS, Port Select
0 = MII mode (default)
1 = ENDEC mode
DRO, Disable Receive Own. This bit should always be cleared to a logic 0 for full-duplex operation and any
loopback operating modes other than “normal mode.”
0 = MAC receives all packets given by the PHY (default)
1 = MAC disables reception of frames during frame transmission (TX_EN = 1)
OM[1:0], Loopback Operating Mode
00 = normal mode, no loopback (default)
01 = internal loopback through MII
10 = external loopback through PHY
11 = reserved
F, Full-Duplex Mode
0 = half-duplex mode (default)
1 = full-duplex mode
PM, Pass All Multicast
0 = multicast frames filtered according to current multicast filter mode (default)
1 = pass all multicast frames; filter-fail bit is reset (= 0) for all multicast frames received
PR, Promiscuous Mode
0 = promiscuous mode disabled
1 = promiscuous mode enabled (default)
31
23
15
7
31
23
15
7
DRO
HO
RA
0
0
0
0
BLOMT[1:0]
BLE
MAC Control
00h
—
0
0
0
0
OM[1:0]
HP
DC
—
0
0
0
0
HBD
LCC
—
F
0
0
0
0
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DBF
PM
PS
TE
0
0
0
0
DRTY
PR
RE
—
0
1
0
0
—
—
—
IF
0
0
0
0
ASTP
PB
—
—
0
0
0
0
24
16
8
0
24
16
8
0