DS80C400 Maxim, DS80C400 Datasheet - Page 89

• Manufacturer Part Number: DS80C400
• Description: The DS80C400 network microcontroller offers the highest integration available in an 8051 device
• Manufacturer: Maxim

Table 27
periods from 3.28ms (2
default setting of CD1:0 (= 10). This wide variation in timeout periods allows very flexible system implementation.
In a typical initialization, the user selects one of the possible counter values to determine the timeout. Once the
counter chain has completed a full count, hardware sets the interrupt flag (WDIF = WDCON.3). Regardless of
whether the software makes use of this flag, there are then 512 system clocks left until the reset flag (WTRF =
WDCON.2) is set. Software can enable (1) or disable (0) the reset using the enable watchdog timer reset (EWT =
WDCON.1) bit.
Table 27. Watchdog Timeout Values
IrDA Clock
The DS80C400 has the ability to generate an output clock (CLKO) as a secondary function on port pin P3.5.
Setting both the IrDA clock-output enable bit (IRDACK:COR.7) and external clock-output enable bit
(XCLKOE:COR.1) to a logic 1 produces an output clock of 16 times the programmed baud rate for serial port 0.
This 16X output clock used in conjunction with serial port 0 I/O (TXD0, RXD0) conveniently allows for direct
connection to common IrDA encoder/decoder devices. If the XCLKOE bit alone is set to logic 1, the CLKO pin
outputs the system clock frequency divided by 2, 4, 6, or 8 as defined by clock-output divide bits (COD1:0). Setting
the IRDACK bit alone to logic 1 has no effect.
Interrupts
The microcontroller provides 16 interrupt sources with three priority levels. All interrupts, with the exception of the
power-fail interrupt, are controlled by a series combination of individual enable bits and a global interrupt enable EA
(IE.7). Setting EA to a 1 allows individual interrupts to be enabled. Clearing EA disables all interrupts regardless of
their individual enable settings.
The three available priority levels are low, high, and highest. The highest priority level is reserved for the power-fail
interrupt only. All other interrupts have individual priority bits that when set to a 1 establish the particular interrupt
as high priority. In addition to the user-selectable priorities, each interrupt also has an inherent natural priority, used
to determine the priority of simultaneously occurring interrupts. The available interrupt sources, their flags, enables,
natural priority, and available priority selection bits are identified in
the 1-Wire bus master share a common interrupt vector (43h). Also note that external interrupt 5 and the 1-Wire
bus master interrupt are multiplexed to form a single interrupt request. When the 1-Wire bus master interrupt is
enabled (EOWMI = 1), it takes priority over external interrupt 5. In order for external interrupt 5 request to be used,
the 1-Wire bus master interrupt must be disabled (EOWMI = 0).
4X/2X CD1:0
1
0
x
x
x
demonstrates that, for a 40MHz crystal frequency, the watchdog timer is capable of producing timeout
00
00
01
10
11
WD1:0 = 00
2
2
2
2
2
15
16
17
17
25
17
x 1/40MHz) to greater than one and a half seconds (1.68 = 2
WATCHDOG INTERRUPT TIMEOUT
WD1:0 = 01
2
2
2
2
2
18
19
20
20
28
WD1:0 = 10
89 of 97
2
2
2
2
2
21
22
23
23
31
Table
WD1:0 = 11
2
2
2
2
2
24
25
26
26
34
28. Note that external interrupts 2–5 and
26
x 1/40MHz) with the