DS80C400 Maxim, DS80C400 Datasheet - Page 34

• Manufacturer Part Number: DS80C400
• Description: The DS80C400 network microcontroller offers the highest integration available in an 8051 device
• Manufacturer: Maxim

DS80C400 Network Microcontroller
with the changes. Note that a machine cycle now requires just 4 clocks, and provides one ALE pulse per cycle.
Most instructions require only one or two cycles, but some require as many as four or five. Refer to the High-Speed
Microcontroller User’s Guide and High-Speed Microcontroller User’s Guide: Network Microcontroller Supplement
for individual instruction-timing details and for calculating the absolute timing of software loops. Also remember that
the counter/timers default to run at the traditional 12 clocks per increment. This means that timer-based events still
occur at the standard intervals, but that code now executes at a higher speed relative to the timers. Timers
optionally can be configured to run at the faster 4 clocks per increment to take advantage of faster controller
operation.
Memory interfacing can be performed identically to the standard 80C32. The high-speed nature of the DS80C400
core slightly changes the interface timing, and designers are advised to consult the timing diagrams in this data
sheet for more information.
This data sheet provides only a summary and overview of the DS80C400. Detailed descriptions are available in the
corresponding user’s guide. This data sheet assumes a familiarity with the architecture of the standard 80C32. In
addition to the basic features of that device, the DS80C400 incorporates many new features.
PERFORMANCE OVERVIEW
The DS80C400’s higher performance comes not just from increasing the clock frequency but from a more efficient
design. This updated core removes the dummy memory cycles that are present in a standard, 12 clock-per-
machine cycle 8051. In the DS80C400, a machine cycle requires only 4 clocks. Thus the fastest instruction, 1
machine cycle in duration, executes three times faster for the same crystal frequency. The majority of instructions
on the DS80C400 experience a 3-to-1 speed improvement, while a few execute between 1.5 and 2.4 times faster.
One instruction, INC DPTR, actually executes in fewer machine cycles (1 machine cycle vs. 2 machine cycles
originally required), thus it sees a 6X throughput improvement over the original 8051. Regardless of specific
performance improvements, all instructions are faster than the original 8051.
Improvement of individual programs depend on the actual mix of instructions used. Speed-sensitive applications
should make the most use of instructions that are at least three times faster. However, given the large number of 3-
to-1 improved op codes, dramatic speed improvements are likely for any arbitrary combination of instructions. The
core architectural improvements and the submicron-CMOS design result in a peak instruction cycle of 54ns (18.75
million instructions per second, i.e., MIPS). To further increase performance, auto-increment/decrement and auto-
toggle enhancements have been implemented for the quad data pointer to allow the user to eliminate wasted
instructions when moving blocks of memory.
SPECIAL FUNCTION REGISTERS (SFRS)
SFRs control most special features of the microcontroller. They allow the device to have many new features but
use the standard 8051 instruction set. When writing software to use a new feature, an equate statement defines the
SFR to the assembler or compiler. This is the only change needed to access the new function. The DS80C400
duplicates the SFRs contained in the standard 80C32.
Table 1
shows the register addresses and bit locations. The
High-Speed Microcontroller User’s Guide: Network Microcontroller Supplement contains a full description of all
SFRs.
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