DS80C400 Maxim, DS80C400 Datasheet - Page 32

• Manufacturer Part Number: DS80C400
• Description: The DS80C400 network microcontroller offers the highest integration available in an 8051 device
• Manufacturer: Maxim

FEATURES (continued)

DETAILED DESCRIPTION
The DS80C400 network microcontroller offers the highest integration available in an 8051 device. Peripherals
include a 10/100 Ethernet MAC, three serial ports, a CAN 2.0B controller, 1-Wire Master, and 64 I/O pins. To
enable access to the network, a full application-accessible TCP IPv4/6 network stack and OS are provided in ROM.
The network stack supports up to 32 simultaneous TCP connections and can transfer up to 5Mbps through the
Ethernet MAC. Its maximum system-clock frequency of 75MHz results in a minimum instruction cycle time of 54ns.
Access to large program or data memory areas is simplified with a 24-bit addressing scheme that supports up to
16MB of contiguous memory. To accelerate data transfers between the microcontroller and memory, the
DS80C400 provides four data pointers, each of which can be configured to automatically increment or decrement
upon execution of certain data pointer-related instructions. The DS80C400’s hardware math accelerator further
increases the speed of 32-bit and 16-bit multiply and divide operations as well as high-speed shift, normalization,
and accumulate functions.
With extensive networking and I/O capabilities, the DS80C400 is equipped to serve as a central controller in a
multitiered network. The 10/100 Ethernet media access controller (MAC) enables the DS80C400 to access and
communicate over the Internet. While maintaining a presence on the Internet, the microcontroller can actively
control lower tier networks with dedicated on-chip hardware. These hardware resources include a full CAN 2.0B
controller, a 1-Wire net controller, three full-duplex serial ports, and eight 8-bit ports (up to 64 digital I/O pins).
Instant connectivity and networking support are provided through an embedded 64kB ROM. This ROM contains
firmware to perform a network boot over an Ethernet connection using DHCP in conjunction with TFTP. The ROM
firmware realizes a full, application-accessible TCP/IP stack, supporting both IPv4 and IPv6, and implements UDP,
TCP, DHCP, ICMP, and IGMP. In addition, a priority-based, preemptive task scheduler is also included. The
firmware has been structured so that a MAC address can optionally be acquired from an IEEE-registered DS2502-
E48.
The 10/100 Ethernet MAC featured on the DS80C400 complies with both the IEEE 802.3 MII and ENDEC PHY
interface standards. The MII interface supports 10/100Mbps bus operation, while the ENDEC interface supports
10Mbps operation. The MAC has been designed for low-power standard operation and can optionally be placed
into an ultra-low-power sleep mode, to be awakened manually or by detection of a Magic Packet or wake-up frame.
Incorporating a buffer control unit reduces the burden of Ethernet traffic on the CPU. This unit, after initial
Advanced Power Management
Energy Saving 1.8V Core
3.3V I/O Operation, 5V Tolerant
Power-Management, Idle, and Stop Mode
Ethernet and CAN Shutdown Control for Power
Early Warning Power-Fail Interrupt
Power-Fail Reset
PIN
100
19
99
Operations with Switchback Feature
Conservation
OWSTP
NAME
MDIO
OW
signal that has no maximum high or low times. The minimum high and low times are 160ns each. The minimum
period for MDC is 400ns independent of the period of TXClk and RXClk.
MII Management Input/Output. The MII management I/O is the data pin for serial communication with the
external Ethernet PHY controller. In a read cycle, data is driven by the PHY to the MAC synchronously with
respect to the MDC clock. In a write cycle, data from the MAC is output to the external PHY synchronously with
respect to the MDC clock.
1-Wire Data, I/O. The 1-Wire data pin is an open-drain, bidirectional data bus for the 1-Wire Bus Master.
External 1-Wire slave devices are connected to this pin. This pin must be pulled high by an external resistor,
normally 2.2kΩ.
Strong Pullup Enable, Output. This 1-Wire pin is an open-drain active-low output used to enable an external
strong pullup for the 1-Wire bus. This pin must be pulled high by an external resistor, normally 10kΩ. This
functionality helps recovery times when the 1-Wire bus is operated in overdrive and long-line standard
communication modes. It can optionally be enabled while the bus master is in the idle state for slave devices
requiring sustained high-current operation.
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
FUNCTION
Enhanced Memory Architecture
Selectable 8/10-Bit Stack Pointer for High-Level
Language Support
1kB Additional On-Chip SRAM Usable as
16-Bit/24-Bit Paged/24-Bit Contiguous Modes
Selectable Multiplexed/Nonmultiplexed External
Merged Program/Data Memory Space Allows In-
Defaults to True 8051-Memory Compatibility
Stack/Data Memory
Memory Interface
System Programming