DS80C400 Maxim, DS80C400 Datasheet - Page 84

• Manufacturer Part Number: DS80C400
• Description: The DS80C400 network microcontroller offers the highest integration available in an 8051 device
• Manufacturer: Maxim

Clock Control
All 1-Wire timing patterns are generated using a base clock of 1.0MHz. To create this base clock frequency for the
1-Wire bus master, the microcontroller system clock must be internally divided down. The clock divisor internal
register implements bits to control this clock division and generation. The prescaler bits (PRE1:PRE0) divide the
microcontroller system clock by 1, 3, 5, or 7 for settings of 00b, 01b, 10b, and 11b respectively. The divider bits
(DIV2:DIV0) control the circuitry, which then divides the prescaler output clock by 1, 2, 4, 8, 16, 32, 64, or 128. The
CLK_EN bit (bit 7 of the clock divisor register) enables or disables the clock generation circuitry. Setting CLK_EN to
a logic 1 enables the clock generation circuitry while clearing the bit disables the clock generation circuitry. The
clock divisor register must be configured properly before any 1-Wire communication can take place.
shows the proper selections for the PRE1:PRE0 and DIV2:DIV0 register bits for a given microcontroller system
clock. Note that the clock generation circuitry requires that the microcontroller system clock be between 3.2MHz
and 75MHz, preferably with 50% duty cycle.
Table 23. Clock Divisor Register Settings
Transmitting and Receiving Data
All data transmitted and received by the 1-Wire bus master passes through the transmit/receive data buffer
(internal register address xxxxx001b). The data buffer is double-buffered with separate transmit and receive
buffers. Writing to the data buffer connects the transmit buffer to the data bus while reading connects the receive
buffer to the data bus.
The data buffer combination for the transmit interface is composed of the transmit buffer and transmit shift register.
Each of these registers has a flag that can be used as an interrupt source. The transmit buffer empty (TBE) flag is
set when the transmit buffer is empty and ready to accept a new byte of data from the user. As soon as the data
byte is written into the transmit buffer, TBE is cleared. The transmit shift register empty (TEMT) flag is set when the
shift register has no data and is ready to load a new data byte from the transmit buffer. When a byte of data is
transferred into the transmit shift register, TEMT is cleared and TBE becomes set.
To send a byte of data on the 1-Wire bus, the user writes the desired data to the transmit buffer. The data is moved
to the transmit shift register, where it is shifted serially onto the 1-Wire bus, least significant bit first. When the
transmit shift register is empty, new data is transferred from the transmit buffer (if available) and the serial process
repeats. Note that the 1-Wire protocol requires a reset before any bus communication.
The data buffer combination for the receive interface is composed of the receive buffer and the receive shift
register. The receive registers can also generate interrupts. The receive shift register full (RSRF) flag is set at the
start of data being shifted into the register, and is cleared when the receive shift register is empty. The receive
buffer full (RBF) flag is set when data is transferred from the receive shift register into the receive buffer and is
cleared after the CPU reads the register. If RBF is set, and another byte of data is received in the receive shift
FREQUENCY (MHz)
10.0
12.0
14.0
16.0
20.0
24.0
28.0
32.0
40.0
48.0
56.0
64.0
MIN
4.0
5.0
6.0
7.0
8.0
SYSTEM CLOCK
< 10.0
< 12.0
< 14.0
< 16.0
< 20.0
< 24.0
< 28.0
< 32.0
< 40.0
< 48.0
< 56.0
< 64.0
< 5.0
< 6.0
< 7.0
< 8.0
MAX
75.0
DIVIDER
RATIO
10
12
14
16
20
24
28
32
40
48
56
64
4
5
6
7
8
DIV2:DIV0
010
000
001
000
011
001
010
001
100
010
011
010
101
011
100
011
110
84 of 97
DIVIDE BITS
SELECTION
16
32
16
64
4
1
2
1
8
2
4
2
4
8
4
8
8
PRE1:PRE0
00
10
01
11
00
10
01
11
00
10
01
11
00
10
01
11
00
PRESCALER
SELECTION
BITS
1
5
3
7
1
5
3
7
1
5
3
7
1
5
3
7
1
Table 23