DS80C400 Maxim, DS80C400 Datasheet - Page 85

• Manufacturer Part Number: DS80C400
• Description: The DS80C400 network microcontroller offers the highest integration available in an 8051 device
• Manufacturer: Maxim

DS80C400 Network Microcontroller
register, the receive shift register holds the new byte and waits until the user reads the receive buffer, clearing the
RBF flag. Thus, if both RSRF and RBF are set, no further transmissions should be made on the 1-Wire bus, or else
data can be lost, as the byte in the receive shift register is overwritten by the next received data.
To read data from a slave device, the bus master must first be ready to transmit data depending on commands in
the command register already set up by the CPU. Data is retrieved from the bus in a similar fashion to a write
operation. The CPU initiates a read operation by writing FFh data to the transmit buffer. The data that is then
shifted into the receive shift register is the wired-AND of the bus master write data (FFh) and the data from the
slave device. When the receive shift register is full, the data is transferred to the receive buffer (if RBF = 0), where
it can be read by the CPU. Additional bytes can be read by sending FFh again. If the slave device is not ready to
respond to read request, the data received the by the bus master is identical to that which was transmitted (FFh).
Bus Master Commands
The 1-Wire bus master can generate special commands on the 1-Wire bus in addition to transmitting and receiving
data. These commands are generated through the setting of a corresponding bit in the command register
(xxxxx000h). These operational modes are defined in The Book of iButton Standards available on our website at
www.maxim-ic.com/iButtonBook.
1WR (Bit 0): 1-Wire Reset. Setting this bit to logic 1 causes a reset of the 1-Wire bus, which must precede any
command given on the bus. Setting this bit also automatically clears the SRA bit. The 1WR bit is automatically
cleared as soon as the 1-Wire bus reset completes. The bus master sets the presence-detect interrupt flag (PD)
when the reset is completed and sufficient time for a 1-Wire reset to occur has passed. The result of the 1-Wire
reset is placed in the interrupt register bit PDR. If a presence-detect pulse was received, PDR is cleared; otherwise,
it is set.
SRA (Bit 1): Search ROM Accelerator. Setting this bit to logic 1 places the bus master into search-ROM-
accelerator mode in order to expedite the search ROM process. The general principle of the search ROM process
is to deselect one device after another at every conflicting ROM ID bit position of the attached slave devices. Using
the search ROM process, the bus master can ultimately learn the ROM ID for each device attached to the 1-Wire
bus. To prevent the CPU from having to perform many bit manipulations during a search ROM process, the search-
ROM-accelerator mode can be invoked, allowing the CPU to send 16 bytes of data to complete a single search
ROM pass. Details about the search ROM algorithm can be found in The Book of iButton Standards or the High-
Speed Microcontroller User’s Guide: Network Microcontroller Supplement.
FOW (Bit 2): Force OW Line Low. Setting this bit to logic 1 forces the OW line to a low value if the EN_FOW bit in
the control register is also set to logic 1. The FOW bit has no affect on the OW line when the EN_FOW bit is
cleared to logic 0.
OW_IN (Bit 3): OW Line Input. This bit always reflects the current logic state of the OW line.
Bus Master Controls
The 1-Wire bus master can perform certain special functions to support OW line operation. These special functions
can be configured through the control register (xxxxx101h).
LLM (Bit 0): Long Line Mode. This bit is used to enable the long-line mode timing. Setting this bit to logic 1
effectively moves the ‘write one’ release and data-sample timing during standard mode communication out to 8µs
and 22µs, respectively. The recovery time is extended to 14µs. This provides a less strict environment for long line
transmissions. Clearing this bit to logic 0 leaves the ‘write one’ release, data sampling, and recovery time (during
standard mode communication) at 5µs, 15µs, and 10µs, respectively.
PPM (Bit 1): Presence Pulse Masking. This bit is used to enable/disable the presence pulse-masking function.
Setting this bit to logic 1 causes the bus master to initiate the beginning of a presence pulse during a 1-Wire reset.
This enables the master to prevent the larger amount of ringing caused by slave devices pulling the OW line low. If
the PPM bit is set, the PDR result bit in the interrupt flag register is always set, indicating that a slave device is
present on the OW line (even if there are none). Clearing the PPM bit to logic 0 disables the presence pulse-
masking function.
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