DS80C400 Maxim, DS80C400 Datasheet - Page 5

• Manufacturer Part Number: DS80C400
• Description: The DS80C400 network microcontroller offers the highest integration available in an 8051 device
• Manufacturer: Maxim

Note 1: Specifications to -40°C are guaranteed by design and not production tested.
Note 2: For a MOVX read operation, on the falling edge of ALE, Port 0 is held by a weak latch until overdriven by external memory.
Note 3: All parameters apply to both commercial and industrial temperature operation, unless otherwise noted.
Note 4: CST is the stretch cycle value as determined by the MD2, MD1, and MD0 bits of the CKCON register. t
Note 5: All signals characterized with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN, RD, and WR with 100pF. The following
Note 6: References to the XTAL, XTAL1, or CLK signal in timing diagrams are to assist in determining the relative occurrence of events, not for
Data Float After RD (P3.7 or
PSEN) High
ALE Low to Valid Data In
Port 0 Address to Valid Data
In
Port 2, 4, 6 Address, Port 4
CE, or Port 5 PCE to Valid
Data In
ALE Low to (RD or PSEN) or
WR Low
Port 0 Address to (RD or
PSEN) or WR Low
Port 2, 4 Address, Port 4 CE,
Port 5 PCE, to (RD or PSEN)
or WR Low
Data Valid to WR Transition
Data Hold After WR High
RD Low to Address Float
(RD or PSEN) or WR High to
ALE
(RD or PSEN) or WR High to
Port 4 CE or Port 5 PCE
High
PARAMETER
periods associated with the internal system clock and are related to the external clock. See the System Clock Time Periods table.
signals, when configured for memory interface, are also characterized with 100pF loading: Port 4 (CE0-3, A16–A19), Port 5.4–5.7
(PCE0-3), Port 6.0–6.5 (CE4-7, A20, A21), Port 7 (demultiplexed mode A0–A7).
determing absolute signal timing with respect to the external clock.
SYMBOL
t
t
t
t
t
t
t
t
t
WHLH2
t
t
t
AVDV0
AVDV2
AVWL0
AVWL2
QVWX
WHQX
WHLH
RHDZ
LLDV
LLWL
RLAZ
10t
5t
2t
t
t
CLCL
CLCL
CLCL
CLCL
CLCL
10t
5t
5t
2t
6t
t
2
t
t
t
t
t
CLCL
CHCL
CLCH
CLCL
CLCL
CLCL
CLCL
CLCL
+ t
CLCL
CLCL
CLCL
+ t
+ t
MIN
CLCL
+ t
+ t
0
0
CHCL
CLCH
CHCL
CLCH
- 3
- 3
- 5
- 4
-5
- 3
CLCH
- 7
- 3
- 3
- 6
- 7
- 6
- 5
- 5
- 5
- 5
5 of 97
- 5
(Note 2)
(4 x C
(4 x C
(4 x C
(4 x C
(4 x C
(4 x C
5t
2t
3t
t
CLCL
CLCL
ST
CLCL
CLCL
ST
ST
t
3t
5t
ST
ST
+ 10)t
5t
ST
2t
6t
t
CHCL
+ 2)t
t
t
t
CLCL
CLCH
CLCL
+ t
CLCL
CLCL
CLCL
+ t
+ 10)t
CLCL
MAX
CLCL
CLCL
+ t
+ 1) t
+ 5) t
+ t
+ 2)t
19
20
CHCL
7
CHCL
CLCH
CLCH
+ 13
CLCL
+ 4
CLCL
+ 6
+ 6
- 5
- 19
+ 4
+ 6
- 5
- 5
CLCL
CLCL
CLCL
CLCL
+ 13
+ 13
- 19
- 19
+ t
+ t
- 19
- 19
- 19
CLCH
- 19
CLCH
-
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLCL
STRETCH VALUES
, t
CLCH
C
4 ≤ C
4 ≤ C
4 ≤ C
4 ≤ C
1 ≤ C
4 ≤ C
1 ≤ C
4 ≤ C
1 ≤ C
4 ≤ C
1 ≤ C
4 ≤ C
1 ≤ C
4 ≤ C
1 ≤ C
4 ≤ C
1≤ C
1≤ C
1≤ C
1≤ C
0≤ C
ST
C
C
C
C
C
C
C
C
C
C
, t
(MD2:0)
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
CHCL
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= 0
≤ 3
≤ 3
≤ 3
≤ 3
≤ 7
≤ 7
≤ 7
≤ 7
≤ 7
≤ 3
≤ 7
≤ 3
≤ 7
≤ 3
≤ 7
≤ 3
≤ 7
≤ 3
≤ 7
≤ 3
≤ 7
are time