DS80C400 Maxim, DS80C400 Datasheet - Page 57

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DS80C400

Manufacturer Part Number
DS80C400
Description
The DS80C400 network microcontroller offers the highest integration available in an 8051 device
Manufacturer
Maxim
Datasheet

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CSR Register:
Register Address:
Bit Names:
Reset State:
PAUSE[15:0], Pause Time [15:0]. These bits are only valid in full-duplex mode. These 16 bits contain the value
that is passed in the pause time field when a pause-control frame is generated. The format for the pause-control
frame is shown in
PCF, Pass Pause-Control Frame. This bit is valid for full-duplex mode only. This bit instructs the MAC whether or
not to set the packet filter bit for pause-control frames.
0 = MAC decodes (if FCE = 1) but does not set the receive status word packet-filter bit (default)
1 = MAC decodes (if FCE = 1) and sets the packet-filter bit = 1 for pause-control frames
FCE, Flow Control Enable
0 = MAC flow control is disabled (default)
1 = MAC flow control enabled; pause-control frame for full-duplex, back-pressure for half-duplex
BUSY, Flow Control Busy. The BUSY bit is only valid in full-duplex mode. The BUSY bit should read logic 0
before initiating a pause-control frame. The BUSY bit should be set to logic 1 to initiate a pause-control frame.
Upon successful transmission of a pause-control frame, the BUSY bit returns to logic 0.
0 = no pause-control frame currently being transmitted (default)
1 = initiate a pause-control frame
Figure 3. Pause-Control Frame
31
23
15
7
31
23
15
7
PREAMBLE
(7)
0
0
0
0
SFD
(1)
Figure
01 80 C2 00 00 01
Flow Control
1Ch
0
0
0
0
3.
(6)
0
0
0
0
SOURCE ADDRESS
(6)
PAUSE [15:8]
0
0
0
0
PAUSE [7:0]
57 of 97
ETHERNET FRAME
0
0
0
0
88 08
(2)
PCF
00 01
0
0
0
0
PAUSE TIME (2)
DS80C400 Network Microcontroller
FCE
0
0
0
0
(46)
BUSY
0
0
0
0
PAD (42
)
24
16
8
0
24
16
8
0
CRC-32
(4)

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