DS80C400 Maxim, DS80C400 Datasheet - Page 50

• Manufacturer Part Number: DS80C400
• Description: The DS80C400 network microcontroller offers the highest integration available in an 8051 device
• Manufacturer: Maxim

Buffer Control Unit
The buffer control unit (BCU) serves as the central controller of all DS80C400 Ethernet activity. The BCU regulates
CPU read/write activity to the Ethernet controller blocks through a series of SFRs: BCU control (BCUC; E7h), BCU
data (BCUD; E6h), CSR address (CSRA; E4h), and CSR data (CSRD; E3h). These SFRs allows the CPU to issue
commands to the BCU, exchange packet size/location information with the BCU, configure the on-chip Ethernet
MAC, and even communicate with external PHYs through the MII serial-management bus.
Table 13
read (1001b) CSR register command, the CSRA SFR must be configured to address a valid CSR register. For
each CSR register write, the CSRD SFR must be loaded with the data to be written prior to issuing the write
command, whereas on a read, CSRD returns the CSR register data following the read command.
CSR register addresses and functions.
Table 13. Buffer Control Unit Commands
Table 14. CSR Registers
The BCU is responsible for coordinating and reporting status for all data-packet transactions between the Ethernet
MAC and the 8kB packet-buffer memory. The size of the transmit and receive buffers within the 8kB packet-buffer
memory is user-configurable through the EBS (E5h) register. During transmit and receive operations, the BCU
operates according to the user-defined buffer allocation and tracks consumption of receive buffer memory so that a
receive-buffer-full condition can be signaled.
For a receive operation, the BCU first must assess whether there are any open pages in receive buffer memory to
accommodate an incoming packet. If there are not open pages, the receive-buffer-full (RBF; EBS.6) flag is set.
Until the RBF condition is cleared, all incoming frames are missed. If receive buffer memory has open pages, the
received data is stored in the first open page starting at byte offset 4, leaving the first 4 bytes open for packet status
reporting. Receive packets requiring multiple pages are stored in consecutive pages. Note that the receive buffer
operates as a circular queue, with page 0 being the consecutive page to follow the final (n - 1) receive buffer page.
The BCU stores incoming data to receive buffer memory until the transaction is complete or until the reception is
(BCUC.3:BCUC.0)
COMMAND
outlines the commands that can be issued through the BCUC register. Prior to issuing a write (1000b) or
Other
0000
0010
0011
0100
0101
0110
1000
1001
1100
1101
No Operation (default)
Invalidate Current Receive Packet
Flush Receive Buffer
Transmit Request (normal)
Transmit Request (disable padding)
Transmit Request (disable CRC)
Write CSR Register
Read CSR Register
Enable Sleep Mode
Disable Sleep Mode
Reserved
CSR REGISTER ADDRESS
OPERATION
(CSRA)
Other
0Ch
1Ch
2Ch
00h
04h
08h
10h
14h
18h
20h
24h
28h
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MAC Control
Ethernet MAC Physical Address [47:32]
Ethernet MAC Physical Address [31:0]
Multicast Address Hash Table [63:32]
Multicast Address Hash Table [31:0]
MII Address
MII Data
Flow Control
VLAN1 Tag
VLAN2 Tag
Wake-Up Frame Filter
Wake-Up Events Control and Status
Reserved
FUNCTION
Table 14
lists the