DS80C400 Maxim, DS80C400 Datasheet - Page 60

• Manufacturer Part Number: DS80C400
• Description: The DS80C400 network microcontroller offers the highest integration available in an 8051 device
• Manufacturer: Maxim

Media Independent Interface (MII)
The DS80C400 contains an IEEE 802.3 MII-compliant PHY interface. This interface contains two basic blocks. The
MII I/O block provides independent transmit and receive data-path I/O and PHY network-status signal inputs. The
MII management block implements a 2-wire serial communication bus to facilitate PHY register access. The block
diagram in
Figure 4. MII Block Diagram
MII Management Block
The MII management block allows the host to write control data to and read status from any of 32 registers in any
of 32 PHY controllers. The MII management block communicates with external PHY(s) over a 2-wire serial
interface composed of the MDC serial-clock output pin and the MDIO pin that serves as the I/O line for all address
and data transactions. Data (MDIO) is valid on the rising edge of clock (MDC). The MII address (14h) and MII data
(18h) CSR registers, outlined previously in the CSR Register section, are used by the CPU to monitor and control
the 2-wire MII serial bus. A write to the CSR register MII address triggers the read or write operation.
shows the MII management frame format.
Figure 5. MII Management Frame Format
*During a read operation, the external PHY drives the MDIO line low for the second bit of the turnaround field to indicate proper synchronization,
and then drives the 16-bits of read data requested.
READ
WRITE
NOTE: WHEN CONNECTING THE DS80C400 TO AN EXTERNAL PHY, DO NOT CONNECT THE RSTOL TO THE RESET OF THE PHY. DOING SO
MAY DISABLE THE ETHERNET TRANSMIT.
Figure 4
PREAMBLE
111…111
111…111
(32 bits)
EXTERNAL
DEVICE
shows the signals associated with the DS80C400 MII.
PHY
START
(2 bits)
01
01
OP CODE
(2 bits)
RXCLK
RX_DV
10
01
CRS
COL
MDIO
TXCLK
TX_EN
TXD[3:0]
RX_ER
RXD[3:0]
MDC
PHY ADDRESS
60 of 97
PHYA [4:0]
PHYA [4:0]
(5 bits)
RECEIVE, AND FLOW
(
MANAGEMENT
SERIAL INTERFACE
MII I/O BLOCK
BUS TO PHY)
(TRANSMIT,
CONTROL)
BLOCK
MII
REGISTER
PHYR[4:0]
PHYR[4:0]
(5 bits)
PHY
DS80C400 Network Microcontroller
DS80C400
AROUND
(2 bits)
TURN
ZZ
10
*
PHYD[15:0]
ZZ….ZZ
(16 bits)
DATA
Figure 5
*
(1 bit)
IDLE
Z
Z