DS80C400 Maxim, DS80C400 Datasheet - Page 61

• Manufacturer Part Number: DS80C400
• Description: The DS80C400 network microcontroller offers the highest integration available in an 8051 device
• Manufacturer: Maxim

DS80C400 Network Microcontroller
MII I/O Block
The MII I/O block supports all of the transmit and receive data transactions between the DS80C400 MAC and the
external PHY device as well as monitoring network status signals provided by the PHY.
The transmit interface is composed of TXCLK, TX_EN, and TXD[3:0]. The TXCLK input is the transmit clock
provided by the PHY. For 10Mbps operation, the transmit clock (TXCLK) should be run at 2.5MHz. For 100Mbps,
TXCLK should be run at 25MHz. The TXD[3:0] outputs provide the 4-bit (nibble) data bus for transmitting frame
data to the external PHY. Each transmission begins when the TX_EN output is driven active high, indicating to the
PHY that valid data is present on the TXD[3:0] bus.
The receive interface is composed of RXCLK, RX_DV, RX_ER, and RXD[3:0]. The RXCLK input is the receive
clock provided by the external PHY. This clock (RXCLK) should be run at 2.5MHz for 10Mbps operation and at
25MHz for 100Mbps operation. The RXD[3:0] inputs serve as the 4-bit (nibble) data bus for receiving frame data
from the external PHY. The reception begins when the external PHY drives the RX_DV input high, signaling that
valid data is present on the RXD[3:0] bus. During reception of a frame (RX_DV = 1), the RX_ER input indicates
whether the external PHY has detected an error in the current frame. The RX_ER input is ignored when not
receiving a frame (RX_DV = 0).
The MII also monitors two network status signals that are provided by the external PHY. The CRS (carrier sense)
input is used to assess when the physical media is idle. The COL (collision detect) input is required for half-duplex
operation to signal when a collision has occurred on the physical media.
Ethernet Frames
The basic purpose of the MII I/O block is to deliver and receive Ethernet frames to and from an external PHY,
which controls the physical carrier. The format of the IEEE 802.3 Ethernet frame is shown in
Figure
6.
The preamble (7 Bytes) and start-of-frame delimiter (1 Byte) precede the Ethernet frame as a means of
synchronizing to the start of the frame. The first two fields of the Ethernet frame are the destination address and the
source address, each made up of 6 octets (bytes). The destination address field is the field examined by the
address check block to determine whether the applied address filter criteria is met or not. The two bytes following
the source address contain the Length or Type of frame. For Ethernet II (DIX) frames, these two bytes contain the
Type field and the protocol for that specific frame type is embedded in the Data field. For frames where Length is
specified in these two bytes, a header would typically follow in the Data field to convey type/protocol information for
the frame (i.e., 802.2 or SNAP). Since the maximum Data field length for an Ethernet frame is 1500 Bytes, and all
assigned frame types are greater than this value (1500d = 05DCh), one can easily distinguish whether the field
holds Type or Length, allowing both kinds of frames to co-exist on the network. A special case occurs when the
VLAN tag protocol ID (= 8100h) is encountered where the Length or Type is normally expected. The frame is then
considered to be VLAN tagged. The VLAN frame format is described later.
Figure 6. IEEE 802.3 Ethernet Frame
ETHERNET FRAME
PREAMBLE
SFD
DESTINATION ADDRESS
SOURCE ADDRESS
TYPE/LENGTH
DATA
CRC-32
(6)
(4)
(2)
(7)
(1)
(6)
(46-1500)
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