DS80C400 Maxim, DS80C400 Datasheet - Page 62

• Manufacturer Part Number: DS80C400
• Description: The DS80C400 network microcontroller offers the highest integration available in an 8051 device
• Manufacturer: Maxim

Address Check Block
The address check block of the Ethernet controller monitors the destination address of all incoming packets and
determines whether the address passes or fails the filter criteria configured by CPU. The outcome of this address
filter test, along with bits signaling whether the frame is a broadcast or multicast frame, is reported by the BCU in a
packet’s receive status word.
All incoming frames can be classified as one of three types: unicast, multicast, or broadcast (a special type of
multicast). A unicast frame contains a 0 in the first received bit of the destination address and is intended for a
single node on the network. A multicast frame contains a 1 in the first received bit of the destination address and is
intended for multiple devices on the network. A broadcast frame is a multicast frame containing all 1’s in the
destination address field and is intended for all network devices. Unless specifically disabled through the disable
broadcast frame (DBF) bit in the CSR MAC control register (00h), broadcast frames are always received by the
DS80C400 MAC.
The address filter criteria is established using five bits found in the CSR MAC control register (00h). Three basic
filter possibilities exist: perfect, inverse, and hash. Perfect filtering requires that the destination address perfectly
match the MAC physical address that has been assigned in CSR registers MAC address high (04h) and MAC
address low (08h). Inverse filtering requires that the destination address be anything other than the assigned MAC
physical address. Perfect and inverse filtering are only applied to unicast frames. Hash filtering uses a user-defined
hash table contained in CSR registers multicast address high (0Ch) and multicast address low (10h) to detect a
successful address match.
valid bit combinations and resultant filter modes. Note that some of the address filter mode control bits can instruct
the address check block to automatically pass or fail certain types of frames.
Figure 7. Address Filter Mode Control Bits
CSR Register MAC Control (00h)
31
Table 15. Address Filter Modes
PM
0
0
0
1
0
1
x
FILTER MODE CONTROL BITS
PR
0
0
0
0
0
0
1
IF
0
1
0
0
0
0
0
Figure 7
HO
0
0
0
0
1
1
x
shows the five bits controlling the destination address filter.
HP
0
0
1
x
1
1
x
DESTINATION ADDRESS FILTER CRITERIA
62 of 97
PERFECT
PERFECT
PERFECT
UNICAST
INVERSE
HASH
HASH
PASS (reset default state = 01000b)
IF (MAC Control.17) Inverse Filtering
HP (MAC Control.13) Hash/Perfect Filtering Mode
HO (MAC Control.15) Hash-Only Filtering Mode
PR (MAC Control.18) Promiscuous Mode
PM (MAC Control.19) Pass All Multicast
MULTICAST
HASH
HASH
PASS
PASS
FAIL
FAIL
0
Table 15
gives the