DS80C400 Maxim, DS80C400 Datasheet - Page 87

• Manufacturer Part Number: DS80C400
• Description: The DS80C400 network microcontroller offers the highest integration available in an 8051 device
• Manufacturer: Maxim

Table 24. 1-Wire Bus Master Interrupt Sources
Peripheral Overview (Primary Integrated System Logic)
The DS80C400 provides several of the most commonly needed peripheral functions in microcomputer-based
systems. The DS80C400 offers three serial ports, four timers, a programmable watchdog timer, power-fail reset
detection, and a power-fail interrupt flag. In addition, the microcontroller contains a CAN module for industrial
communication applications. Each of these peripherals is described below, and more details are available in the
High-Speed Microcontroller User’s Guide and the High-Speed Microcontroller User’s Guide: Network
Microcontroller Supplement.
Serial Ports
The microcontroller provides a serial port (UART) that is identical to the 80C52. Two additional hardware serial
ports are provided that are duplicates of the first one. This second port optionally uses pins P1.2 (RXD1) and P1.3
(TXD1). The third port optionally uses pins P6.6 (RXD2) and P6.7 (TXD2). The function of each of the three serial
ports is controlled by the SFRs and bits shown in
Table 25. Serial Port SFRs
All three serial ports can operate simultaneously and be configured for different baud rates or different modes.
When using a timer for the purpose of baud rate generation, serial port 1 must use timer 1, serial port 2 must use
timer 3, while serial port 0 can use either timer 1 or timer 2. Refer to the High-Speed Microcontroller User Guide for
full descriptions of serial port operational modes.
Presence Detect
Transmit Buffer
Empty
Transmit Shift
Register Empty
Receive Buffer Full
Receive Shift
Register Full
1-Wire Short
1-Wire Low
Framing Error-Detection Enable
Slave Address Mask Enable
INTERRUPT
SOURCE
Input/Output Data Buffer
FUNCTION CONTROL
Baud Rate Doubler Bit
Control Register
SERIAL PORT
Slave Address
After a 1-Wire reset has been issued, this flag is set after the amount
of time for a presence-detect pulse to have occurred. This bit is cleared
when the interrupt flag register is read.
This flag is set when the transmit buffer is empty and ready to receive
the next byte. This bit is cleared when data is written to the transmit
buffer. A read of the interrupt flag register has no effect on this bit.
This flag is set when the transmit shift register is empty and is ready to
load a new byte from the transmit buffer. This bit is cleared when data
is transferred from the transmit buffer to the transmit shift register. A
read of the interrupt flag register has no effect on this bit.
This flag is set when there is a byte of data in the receive buffer waiting
to be read. This bit is cleared when the receive buffer is read.
This flag is set when there is a byte of data in the receive shift register
waiting to be transferred to the receive buffer. This bit is cleared when
data in the receive shift register is transferred to the receive buffer.
This flag is set when the OW line was low before the bus master was
able to send out the beginning of a reset or a time slot. A read of the
interrupt flag register clears this bit.
This flag is set when the OW line is low while the bus master is idle,
signaling that a slave device has issued a presence pulse on the OW
line. A read of the interrupt flag register clears this bit if the OW line is
no longer low while the master is idle.
SERIAL PORT 0
SADEN0
SADDR0
PCON.7
PCON.6
SCON0
SBUF0
MEANING
Table
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25.
SERIAL PORT 1
WDCON.7
SADEN1
SADDR1
PCON.6
SCON1
SBUF1
SERIAL PORT 2
SADEN2
SADDR2
PCON.6
T3CM.4
SCON2
SBUF2
ENABLE/FLAG LOCATION
Interrupt Enable Register.x)
(Interrupt Flag Register.x
Bit 0
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7